Nvidia Corporation

Other

Lingfeng Yuan

David Brian Glasco

John Stephen Montrym

John H Edmondson

James M Van Dyke

Brian D Hutsell

Robert C Keller

A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for coordinating context memory storage block binds and independently controlling access to the context memory without interference from other engine activities. In one exemplary implementation the context information is included in a block and the memory management unit binds the block to instance memory. The instance memory can be protected memory. The instance memory can also support multiple channels associated with the plurality of engines. In one exemplary implementation, the instance memory includes a pointer to a page table. The instance memory can also include context save and restore data and each one of the plurality of engines initiates a unique block bind by indicating an association between their engine ID and a given block of instance memory.

Memory access management block bind system and method

A memory access technique, in accordance with one embodiment of the present invention, includes caching page size data for use in accessing a set-associative translation lookaside buffer (TLB). The technique utilizes a translation lookaside buffer data structure that includes a page size table and a translation lookaside buffer. Upon receipt of a memory access request a page size is looked-up in the page size table utilizing the page directory index in the virtual address. A set index is calculated utilizing the page size. A given set of entries is then looked-up in the translation lookaside buffer utilizing the set index. The virtual address is compared to each TLB entry in the given set. If the comparison results in a TLB hit, the physical address is received from the matching TLB entry.

Memory access techniques utilizing a set-associative translation lookaside buffer

A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.

Compressed data access system and method

A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example a memory store information and instructions for the engines. The shared resource management unit independently caches and invalidates page table entries on a per engine basis.

System and method for independent invalidation on a per engine basis

A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.

System and method for concurrently managing memory access requests

A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.

Techniques for servicing fetch requests utilizing coalesing page table entries

A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced mappings are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can cache a single coalesced mapping and not all of them. The single cached coalesced mapping may be used to translate all of the virtual addresses to physical addresses for the corresponding contiguous memory space.

Memory access techniques including coalesing page table entries

A shared resource management system and method are described. In one embodiment, a shared resource management system facilitates age based miss replay. In one exemplary implementation, a shared resource management system includes a plurality of engines, and a shared resource a shared resource management unit. The plurality of engines perform processing. The shared resource supports the processing. The shared resource management unit handles multiple outstanding miss requests.

Age based miss replay system and method

A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate access to memory while controlling translation between virtual and physical memory 'spaces'. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space. The fill component tracks the status of an access request progress from a plurality of engines independently and faults that occur in attempting to access a memory space.

Override system and method for memory access management

A memory access technique, in accordance with one embodiment of the present invention, includes caching segmentation data. The technique utilizes a separate memory for storing a plurality of context specifiers and an MMU. The MMU includes an on-chip cache and a segmentation unit. The MMU receives a location of a particular context specifier and a corresponding context index for each of one or more of the plurality of context specifiers stored in the separate memory. The segmentation unit retrieves the particular context specifier and caches it locally. The segmentation unit also binds the cache location of the particular context specifier to the corresponding context index. After caching one or more context specifiers and generating a corresponding binding, the segmentation unit may receive a memory access request that includes a given context index. A given context specifier that is cached locally is accessed by the segmentation unit using the context index to get a base address. The base address from the given context specifier is utilized by the segmentation unit to generate a virtual address for the memory access request.

Direct memory access techniques that include caching segmentation data

A technique for caching page access parameters, in accordance with one embodiment of the present invention, includes translating a given virtual address to a particular physical address using an address translation data structure. One or more page access parameters related to the particular physical address is stored in a separate page access data structure. The technique may further include accessing the page access data structure to manage access to memory as a function of the page access data.

Growing community of inventors

Palo Alto, CA, United States of America

Lingfeng Yuan