Nvidia Corporation

Lingfei Deng

Ge Yang

Hwong-Kwo Lin

Xi Zhang

Jiani Yu

A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion

Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

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Lingfei Deng