Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Ling-Yen Yeh

Chih-Sheng Chang

Clement Hsingjen Wann

Carlos H Diaz

Chi-Yuan Shih

Yee-Chia Yeo

Cheng-Yi Peng

Chun-Chieh Lu

Chi-Wen Liu

Wilman Tsai

Meng-Hsuan Hsiao

Chien-Hsing Lee

Wei-Chun Tsai

Yuan-Chen Sun

Yen-Yu Chen

Tung-Ying Lee

Tung Ying Lee

Chia-Wen Chang

Yi-Tang Lin

Meng-Chun Chang

Li-Chi Yu

Yuan-Fu Shao

Tze-Liang Lee

Tzu-Chiang Chen

Cheng-Hsien Wu

I-Sheng Chen

Yasutoshi Okuno

Wei-Sheng Yun

Winnie Victoria Wei-Ning Chen

Hong-Nien Lin

Chih-Hao Wang

Chin-Hsiang Lin

Chun Hsiung Tsai

Ming-Hua Yu

Neng-Kuo Chen

Sey-Ping Sun

Gin-Chen Huang

Yen-Chun Huang

Hao-Hsiung Lin

Ta-Chun Ma

Che-Wei Yang

Yu-Ming Lin

Yu-Lien Huang

Hun-Jan Tao

Ting-Chu Ko

Wen-Huei Guo

Chung-Hsien Chen

Hung-Yao Chen

Mong-Song Liang

Liang-Gi Yao

Chine-Gie Lou

Hao-Ming Lien

Yusuke Oniki

Jyh-Chyurn Guo

Ming-Han Liao

Wei-Shan Hu

Chao Hsiung Wang

Jim Cy Huang

Kai-Ting Tseng

Ih-Chin Chen

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Method of manufacturing a semiconductor device

A semiconductor structure is provided. The semiconductor structure includes a first nanowire over a semiconductor fin. The semiconductor structure also includes a second nanowire over the first nanowire and a third nanowire over the second nanowire. The semiconductor structure further includes a source/drain wrapping around the first nanowire, the second nanowire and the third nanowire. A thickness of a first portion of the source/drain vertically sandwiched between the first nanowire and the second nanowire is different from a thickness of a second portion of the source/drain vertically sandwiched between the second nanowire and the third nanowire.

Semiconductor structure

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.

Multi-gate semiconductor device and method for forming the same

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Integrated circuit structure and method with solid phase diffusion

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.

Method of manufacturing semiconductor device including ferroelectric layer having nano crystals

A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.

In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Method for forming integrated semiconductor device with 2D material layer

The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.

Local epitaxy nanofilms for nanowire stack GAA device

A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

Semiconductor device and fabricating method thereof

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

Growing community of inventors

Hsinchu, Taiwan

Ling-Yen Yeh