Mediatek Corporation

Mediatek Incorporation

Ling-Wei Ke

Hsin-Hung Chen

Tao Cheng

Ching-Chung Ko

Tien-Yueh Liu

Tser-Yu Lin

Peng-Cheng Kao

Tai-Yuan Yu

Ta-Hsi Chou

Tai Yuan Yu

Ping-Ying Wang

Chi-Kun Chiu

Bing-Yu Hsieh

Chang-Fu Kuo

Shin-Fu Chen

Shou-Tsung Wang

Kuang-Kai Teng

Jen-Chiou Bo

Ming-Fong Lei

An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

Power and ground routing of integrated circuit devices with improved IR drop and chip performance

An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

A transforming circuit includes: a first winding having a first port and a second port operably coupled for a differential signal; and a plurality of second windings, each having a third port and a fourth port operably coupled for a single-ended signal when magnetically coupled to the first winding. When one of the second windings is magnetically coupled to the first winding, each remaining second winding(s) is not magnetically coupled to the first winding.

Transforming circuit

A signal transforming circuit includes: a first substantially 8-shaped geometry primary winding arranged to couple a first input signal; and a substantially 8-shaped geometry secondary winding having a first port and a second port, the substantially 8-shaped geometry secondary winding disposed adjacent to the first substantially 8-shaped geometry primary winding to magnetically couple to the first substantially 8-shaped geometry primary winding for generating an output signal at the first port and the second port.

Signal transforming circuit

A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

PLL with loop bandwidth calibration circuit

A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Signal generating apparatus and method thereof

A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator. The modulation processor generates the processed input modulation signal to adjust the division factor of the frequency dividing unit and compensating for distortion induced by the frequency regenerator.

Phase locked loop frequency synthesizer and method for modulating the same

A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Phase locked loop frequency synthesizer

A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor having a first size and coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor having a second size being different than the first size and coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.

Fast-disabled voltage regulator circuit with low-noise feedback loop and operating method thereof

A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal, wherein the phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode; a detecting device for detecting the synthesized signal to generate a calibrating signal in the calibration mode; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered signal; and a modulating device for modulating the filtered signal to generate the dividing factor.

A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

Phase lock loop applying in wireless communication system and method thereof

A programmable frequency divider for dividing the frequency of a source signal according to a selectable divisor which is obtained based on a plurality of divisor signals and outputting a result signal having a divided frequency includes at least one cell of a first type. The cells of the first type are cascaded with each other. The programmable frequency divider synchronously resets all of the cells of the first type according to a reset signal in order to selectively switch each cell of the first type to perform a divide-by-two or divide-by-three operation according to a corresponding divisor signal. The last cell of the first type outputs the result signal having the divided frequency.

Multi-modulus programmable frequency divider

A low-noise voltage regulator circuit with quick disablement is disclosed. The voltage regulator circuit includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.

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Hsin-Chu Hsien, Taiwan

Ling-Wei Ke