Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Semiconductor Manufacturing Corp.

Ling-Sung Wang

Chi-Yen Lin

Ru-Shang Hsiao

Chih-Hsun Lin

Chao-Hsuing Chen

Mei-Hsuan Lin

Chen-Chieh Chiang

Chih-Kang Chao

Yu-Jen Chen

I-Shan Huang

Chih-Mu Huang

Chan-yu Hung

Jiun-Jie Huang

Ching-Hwanq Su

Jen-Pan Wang

Jung-Chi Jeng

Pin Chia Su

Wen-Hsi Lee

Ying Hsin Lu

Kun-Ei Chen

Ching-Hua Chu

Ying-Han Chiou

Chih-Fu Chang

Jyh-Ren Wu

Ying-Lin Chen

Hsueh-Han Lu

Cheng-You Tai

Kun-ei Chen

Chien-Jung Wang

Ko-Hsing Chang

Sung-Hsin Yang

Chingfu Lin

Chia-Chen Liu

Chia-Ming Chang

Chun-Ying Wang

Cing-Yao Chan

Tsung Jing Wu

Hsu Tung Yen

Bo Hsiang Huang

Chiang-Lang Yen

Chih-Chan Lu

Jen-Yi Chen

Yung-Yao Wang

Huang Jiun-Jie

Chih-Ming Chen

Yung-Chang Chang

I-Chih Chen

Ying-Hao Chen

Wen-Chang Kuo

Jun-Nan Nian

Yi-Ting Chen

Min-San Huang

Yao-Tsung Chen

I-i Cheng

Wei-Barn Chen

Kuan-Yu Chen

Wen Han Hung

Tzu Kai Lin

Kern-Huat Ang

Chao-Tzung Tsai

Yu-Hong Pan

Chi-An Kao

Jia-Yang Ko

Chan-Yu Hung

Ru-shang Hsiao

Horng-Ming Lee

Hung Pin Chen

Yi-Chung Lin

Ching Lang Yen

Ming-Tsang Tsai

Huan-Kuan Su

Yi Ping Chao

Kun Da Jhong

Ching Kang Chen

Zhi-hong Chung

Wei-Cheng Chen

Pei-lum Ma

Jia-Ming Huang

Jia Yang Ko

Wei-Chun Liao

Guo-Zhou Huang

Chen-Hsi Lin

Ching-Chien Huang

Huan-Sung Fu

Yong-Kang Wang

Shung-Bing Yang

Yu-Ping Chang

A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.

Semiconductor structure including 3D capacitor and method for forming the same

A system for monitoring a wafer carrier includes an overhead hoist transport (OHT) vehicle, a scanner, and a processer. The OHT vehicle is configured to transport the wafer carrier along a vertical direction. The scanner is disposed below the OHT vehicle, wherein the wafer carrier is transported vertically by the OHT vehicle to pass through the scanner, and the scanner at least scans a lower portion of the wafer carrier along a horizontal direction and an upper portion of the wafer carrier along the horizontal direction. The processor is coupled to the scanner, wherein the processer receives a scanning result from the scanner after the wafer carrier is scanned, and the scanning result includes information of a gas composition within the wafer carrier. A method of manufacturing a semiconductor structure including a scanning procedure is also provided.

System for monitoring wafer carrier and method of manufacturing semiconductor structure

A container for receiving a semiconductor device is provided. In one embodiment, the wafer holder assembly includes a first wafer holder with a plurality of first fingers arranged in a first common horizontal plane and a second wafer holder with a plurality of second fingers arranged in a second common horizontal plane. The first wafer holder and the second holder are configured to move relative to each other in a vertical direction, and the first wafer holder and the second holder are configured to rotate relative to each other around a vertical axis.

Wafer holder assembly

The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Circuit structure with gate configuration

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.

Manufacturing method of semiconductor structure and semiconductor structure thereof

A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.

Semiconductor device

A semiconductor device and method of manufacturing that includes a first etch stop layer and a second etch stop layer to prevent delamination and damage to underlying components. A first passivation layer and a second passivation layer are disposed on a substrate, with a metal pad exposed through the passivation layers and contacting a top metal component of the substrate. The first etch stop layer is then formed on the second passivation layer and the metal pad. A third passivation layer is then formed on the substrate with an opening to the metal pad, which is covered by the first etch stop layer. The second etch stop layer is then formed on the third passivation layer and in the opening on the second etch stop layer. A bottom metal film/conductive component is then formed on the second etch stop layer, photoresist is applied, and wet etching is performed. The metal pad is protected from damage caused by delamination of the second etch stop layer by the first etch stop layer.

Semiconductor device and method of manufacture

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A first layer is formed over a first region and a second region of a substrate. A first etching is performed on the first layer, thereby forming a first trench in the first region and a second trench in the second region. A first amorphization is performed on the first layer in the second region. A second etching is performed on the first layer, wherein an etching rate of the second etching in the second region is greater than an etching rate of the second etching in the first region.

Method for manufacturing through vias using amorphization to adjust etching rate

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

Semiconductor devices and methods for increased capacitance

A semiconductor structure and a method are provided. The method includes patterning a substrate to form a first fin structure in a first region and a second fin structure in a second region, wherein a first width of the first fin structure is greater than a second width of the second fin structure; forming a protecting layer on the second fin structure; and forming a first oxide layer over the first fin structure and forming a second oxide layer over the protecting layer, wherein a width of the first oxide layer is greater than a width of the second oxide layer.

Semiconductor structure and forming method thereof

A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

Semiconductor device including unilaterally extending gates and method of forming same

A work piece holder provided herein includes a support baffle and an elevating element. The support baffle extends along an arc path. The elevating element is disposed on the support baffle and is pivoted to be movable between an unlock status and a lock status.

Work piece holder and method of transferring a work piece

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Gate electrode having a work-function layer including materials with different average grain sizes

Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Semiconductor device structure and methods of forming the same

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Tainan, Taiwan

Ling-Sung Wang