Macronix International Co., Ltd.

Ling Kuey Yang

Lan Ting Huang

Po Hsuan Wu

Chen-Chin Liu

Chen Chin Liu

A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate

A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.

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Changhua, Taiwan

Ling Kuey Yang