United Microelectronics Corp.

Ling-Hsiu Chou

Ping-Chia Shih

Chi-Cheng Huang

Chien-Hung Chen

Yu-Chun Chen

Ya-Sheng Feng

Kuo-Lung Li

Hsiang-Chen Lee

Chia-Wen Wang

Kun-I Chou

Yu-Chun Chang

Hung-Wei Lin

An-Hsiu Cheng

Chia-Hui Huang

Chih-Yang Hsu

Shao-Nung Huang

Wei-Pin Huang

Jen-Yang Hsueh

Tseng-Fang Dai

Jheng-Jie Huang

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Method of programming MLC memory device and related MLC memory device

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

Semiconductor device and manufacturing method thereof

A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

Method for manufacturing silicon&#x2014;oxide&#x2014;nitride&#x2014;oxide&#x2014;silicon (SONOS) non-volatile memory cell

A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.

Method for fabricating non-volatile memory semiconductor device

Growing community of inventors

Tainan, Taiwan

Ling-Hsiu Chou