Omnivision Technologies, Inc.

Ling Fu

Tiejun Dai

Zhe Gao

Yu-Shen Yang

Qing Qin

Rui Wang

Hiroaki Ebihara

Zheng Yang

Zhiyong Zhan

Jiayu Guo

Tomas Geurts

A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

CAPMID design in VRFD for HDR structure

An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

Real GS and OFG timing design for 1-by-2 shared HDR VDGS

A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

Voltage domain global shutter readout circuit timing

A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

Voltage domain global shutter readout circuit

A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Sample and hold switch driver circuitry with slope control

A pixel readout circuit includes an analog to digital converter coupled to the bitline output of the pixel circuit. A switch is coupled between the bitline output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter. The switch is pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion. The switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation.

Resettle timing for low power pixel readout

An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

Event driven pixel for spatial information extraction

Switching techniques for fast voltage settling in image sensors are described. In one embodiment, a transfer gate (TX) driver circuit of an image sensor includes a TX driver configured to provide a TX driver voltage to a plurality of pixels of an image sensor. A power supply (NVDD) is operationally coupled to the TX driver. A first switch (SW) operationally coupling an outside capacitance (Cext) and the TX driver. A second switch (SW) operationally coupling the Cext and the NVDD. A third switch (SW) operationally coupling the NVDD and the TX driver. A falling edge of the TX driver voltage is configured to control a start of data transfer from individual pixels of the plurality of pixels. The SWand the SWare configured in an open position before the falling edge of the TX driver voltage. The SWis configured in a closed position before the falling edge.

Switching techniques for fast voltage settling in image sensors

A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

A readout circuit for use in an image sensor includes a first sample and hold (SH) circuit coupled to a bitline that is coupled to a pixel array. A second SH circuit is coupled to the bitline. A bypass switch is coupled to the bitline, the first SH circuit, and the second SH circuit. An analog to digital converter (ADC) is coupled to the bypass switch. The bypass switch is configured to provide an image charge value from the pixel array to the ADC through the bitline, or through one of the first SH circuit or the second SH circuit in response to a switch select signal.

High dynamic range high speed CMOS image sensor design

An image sensor includes pixel circuitry with a photodiode to receive light and output a pixel signal. The image sensor also includes readout circuitry with a first sample and hold transistor coupled to the pixel circuitry, and a first capacitor coupled to the first sample and hold transistor to receive the pixel signal. A second sample and hold transistor is coupled to the pixel circuitry, and a second capacitor is coupled to the second sample and hold transistor to receive the pixel signal. A first output switch is coupled to output the pixel signal from the first capacitor, and a second output switch is coupled to output the pixel signal from the second capacitor. A boost transistor is coupled to connect the first output switch and the second output switch when the boost transistor is turned on.

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Santa Clara, CA, United States of America

Ling Fu