United Microelectronics Corp.

Ling-Chun Chou

Kun-Hsien Lee

I-Chang Wang

Chin-Cheng Chien

Ming-Tsung Chen

Yu-Hung Chang

Ching-Wen Hung

Po-Chao Tsao

Chieh-Te Chen

Shin-Chi Chen

Tsung-Hung Chang

Chun-Yuan Wu

Jiunn-Hsiung Liao

Shu-Yen Chan

Chiu-Hsien Yeh

Shin-Chuan Huang

Ted Ming-Lang Guo

Guang-Yaw Hwang

Kuan-Ti Wang

Pau-Chung Lin

Chih-Sen Huang

Kai-Lin Lee

Hui-Ling Chen

Cheng-Yen Wu

Ting-Yao Lin

Shuen-Cheng Lei

Hsi-Hua Liu

Te-Chi Yen

A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Lateral diffusion metal-oxide semiconductor device

A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

High voltage semiconductor device

A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

Semiconductor structure and manufacturing method thereof

A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

Bipolar junction transistor

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.

Semiconductor device and method for fabricating the same

The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

FinFET structure device

The present invention provides a method of forming a semiconductor device including following steps. Firstly, a fin shaped structure is formed on a substrate, and a gate structure is formed to be across the fin shaped structure. Next, a dielectric layer is formed on the substrate, covering the gate structure, and a gate electrode of the gate structure is removed, to form a first gate trench. Then, a threshold voltage implantation process and a compensated threshold voltage implantation process are sequentially performed in the first gate trench, to implant compensated two dopants respectively. Following these, a work function layer and a conductive layer are formed to fill the first gate trench.

Method of forming semiconductor device

A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.

Gate structure and method for trimming spacers

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Strained silicon structure

A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Spacer scheme for semiconductor device

A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Semiconductor device and manufacturing method thereof

A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Growing community of inventors

Yun-Lin County, Taiwan

Ling-Chun Chou