Yangtze Memory Technologies Co., Ltd.

Ling Chu

Zhipeng Dong

Manxi Wang

Hongtao Liu

Haibo Li

Ying Huang

Ke Liang

Li Xiang

Yue Sheng

Shuang Liu

Min Zhang

Lu Qiu

Haiwen Fang

Sanshan Jiao

In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines and configured to read a select row of the rows of the memory cells. The peripheral circuit includes a word line driver coupled to the select row through a select word line of the word lines and to an unselect row of the rows of the memory cells through an unselect word line of the word lines, and configured to apply a pass voltage to the unselect word line, and discharge the unselect word line from the pass voltage to a first recovery voltage that is greater than a supply voltage of the array of memory cells.

Method for recovery in read operation of memory device and memory device thereof

This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Memory device, a memory system and an operation method

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2levels, where N is an integer greater than 1. The level corresponds to one of 2pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each target memory cell is programmed into one of K intermediate levels based on the corresponding piece of N-bits data, wherein 2&#x3c;K&#x3c;2. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2levels based on the corresponding piece of N-bits data.

Memory device and multi-pass program operation thereof

A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

Negative gate stress operation in multi-pass programming and memory device thereof

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Wuhan, China

Ling Chu