Intel Corporation

Ling Cen

Vivek Garg

Deep K Buch

David Zhao

Vladimir Pentkovksi

Mohan J Kumar

James B Crossland

Shivnandan D Kaushik

Tessil Thomas

Linda J Rankin

Rahul Pal

Binata Bhattacharyya

Baskaran Ganesan

David J O'Shea

Ken C Haren

Binoy Balan

Vishal Moondhra

David O'SHEA

Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.

Store performance in strongly ordered microprocessor architecture

The invention facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.

Two-hop cache coherency protocol

Methods and apparatus to quiesce and/or de-quiesce links (such as point-to-point link) in a multi-processor system are described. In one embodiment, one or more bits are modified to indicate the status of quiesce/dequiesce processes.

Quiescing and de-quiescing point-to-point links

Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Hot plug interface control method and apparatus

In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request in parallel with obtaining data of the speculatively provided read request, and providing the data of the speculatively provided read request to the processor if the read request is coherent. In this way, data may be used by a processor with a reduced latency. Other embodiments are described and claimed.

Speculatively performing read transactions

A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.

Store performance in strongly-ordered microprocessor architecture

Arrangements facilitating ordered transactions, e.g., ordered writes, in a packet switch system having multiple switch elements.

Arrangements facilitating ordered transactions

A system, apparatus, and method for a link layer protocol to utilize a main buffer and share the remaining link units according to a list buffer or FIFO. The system includes an efficient link layer to facilitate transmitting and receiving data and information. The list buffer is used to store the buffer indexes for all the link units for the respective virtual connections.

Method, system, and apparatus for a credit based flow control in a computer system

During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-'OR' bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.

Growing community of inventors

Austin, TX, United States of America

Ling Cen