Adv Antest Corporation

Linden Hsu

Mei-Mei Su

Duane Champoux

Ben Rogel-Favila

Srdjan Malisic

Michael Frank Jones

Chi Yuan

Rotem Nahum

Boilam Phan

Yogen Krishnapillai

Mike Bautista

Camilo Montenegro

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

Diagnostic tool for traffic capture with known signature database

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a system comprising a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the test board includes a functional/interface application specific integrated circuit (ASIC) component, and the test board includes a component configured to generate a simulated indication that a resource from a source external to the functional/interface ASIC is stable, and a tester configured to direct testing of the plurality of DUTs, wherein the tester is communicatively coupled to the functional/interface ASIC. In one embodiment the ASIC is a field programmable gate array (FPGA).

Self-reset testing systems and methods

A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.

Software and firmware support for device interface board configured to allow devices supporting multiple different standards to interface with the same socket

A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Software directed firmware acceleration

A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.

NVMe-MI over SMBus multi-master controller with other SMBus and I2C masters in a single FPGA chip

A method for monitoring a communication link between a device under test (DUT) and automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a DUT using a protocol analyzer module, wherein the data traffic comprises a flow of traffic between the DUT and a protocol core of a programmable logic device, wherein the protocol analyzer module is integrated within the programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, and wherein the protocol core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method further comprises saving results associated with the monitoring in a memory associated with the protocol analyzer module and transmitting the results upon request to an application program executing on the system controller.

Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware

A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Growing community of inventors

San Jose, CA, United States of America

Linden Hsu