Intersil Corporation

Other

Harris Corporation

Linda Susan Brush

John M Neilson

Christopher L Rexer

Louise E Skurkey

John Lawrence Benjamin

Richard Douglas Stokes

Christopher Boguslaw Kocon

Jun Zeng

Jack H Linn

George V Rouse

John J Hackenberg

Anup Bhalla

Frank Stensney

Christopher Boguslow Kocon

Christopher Michael Scarba

John Mannine Savidge Neilson

John Manning Neilson

Christopher Lawrence Rexer

Louis Ellen Skurkey

A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Power trench transistor device source region formation using silicon spacer

A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed on the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge passivation zone comprising a junction termination extension (JTE) JTE region that includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at a point substantially directly beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point, becoming less in both the portions extending away from and beneath the well region.

Doubly graded junction termination extension for edge passivation of semiconductor devices

A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.

Method of making a MOS-gated semiconductor device with a single diffusion

A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

Method of making MOS-gated semiconductor devices

Growing community of inventors

Mountaintop, PA, United States of America

Linda Susan Brush