Advanced Micro Devices Corporation

Linda S Milor

Khoi A Phan

Chun Jiang

Yeng-Kaung Peng

David Ashby Steele

The present invention is a device and method for detecting undesired connection between conductive structures within multiple layers on a semiconductor wafer during fabrication of an integrated circuit on the semiconductor wafer. The present invention includes a first conductive structure fabricated within a first layer on the semiconductor wafer and a second conductive structure fabricated within a second layer on the semiconductor wafer. The present invention also includes an interlevel of an insulating material disposed between the first layer and the second layer for separating the first layer from the second layer. The present invention further includes a contact structure of conductive material disposed within the interlevel of the insulating material. The contact structure is connected to the first conductive structure, and the contact structure becomes undesirably connected to the second conductive structure from at least one of: sufficient misalignment of at least one of the first layer, the second layer, and the interlevel of insulating material; sufficient proximity effect on at least one of the first conductive structure, the second conductive structure, and the contact structure; and sufficient defects in at least one of the second layer and the interlevel of insulating material. In addition, the present invention includes a detector for determining when the contact structure is undesirably connected to the second conductive structure. The first conductive structure may have a comb structure with a respective contact structure connected to each tooth of the comb structure. In that case, the second conductive structure surrounds three sides of the respective contact structure.

Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer

Detection of undesired connection between conductive structures within

A system and method for providing a plurality of interconnects for a microcircuit is disclosed. The microcircuit has a plurality of functional components. The method and system include determining the placement of each of the plurality of functional components and determining a width of each of the plurality of interconnects. The determination of the width is based on a capacitance between each interconnect and a portion of the plurality of interconnects.

Method and system for providing an interconnect layout to reduce delays

Defects in integrated circuit wafers (10) are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps. Defect simulation is used to understand the relation between defects in the wafer (10) and the resulting wafer profiles. Defects such as particles (50) and bubbles (22) in the photoresist (28), for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects.

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Berkeley, CA, United States of America

Linda S Milor