Motorola Corporation

Linda R Nuckolls

Michael C Wood

James Robert Feddeler

James M Sibigtroth

Brian M Millar

Michael I Catherwood

George E Baker

Daniel Mark Thompson

Greg A Racino

Edward M Stellini

Timothy E Barnard

A system comprising a supply voltage isolation module ( ), and a battery detector ( ), both responsive to a battery pin ( ). The system further including a voltage detection module ( ) responsive to a voltage supply pin ( ), where the voltage detection module ( ) compares a supply voltage from the voltage supply pin ( ) to a threshold. The system also including control logic ( ) responsive to the battery detector ( ) and the voltage detection module ( ). Also disclosed are methods for responding to connection of a battery ( ) to a logic device ( ), placing a logic device ( ) into a low power state in response to connection of a battery ( ) to the logic device ( ), and detecting a battery condition for a logic device ( ) having a battery pin ( ).

Methods and systems for detecting and for responding to connection of a battery to a logic device

A method for automatically detecting a programmed status of a non-volatile memory and selecting one of multiple operational modes based on that status. In one embodiment a non-volatile memory (102) has a normal and an access restricted operational mode. The memory is placed in the access restricted operational mode once it is programmed in order to prevent unauthorized access to the programmed data. A detection logic (226) determines whether the non-volatile memory is in a non-programmed state. Based on this detection it is determined whether the non-volatile memory is to be placed in a normal or an access restricted operational mode. The invention relates also to determining an operational mode of the microcontroller which can advantageously be incorporated into an assembled electronic device.

Microcontroller having a non-volatile memory and a method for selecting

A data processing system (10) having address pins (30), data pins (31), control pins (32), chip select pins (33), and other pins (34). For bus cycles of an instruction which do not require use of an external address bus (35), the values driven by the address pins (30) are 'frozen' in their previous logic state. The previous logic state is determined by the most recent value driven by address pins (30) during a bus cycle that required use of the external address bus (35). Data pins (31) may be 'frozen' in the same manner as address pins (30). Control pins 32, chip select pins 33, and other pins 34 may be driven to their respective inactive logic states. The goal is to reduce noise and power consumption by reducing the voltage level switching taking place on external conductors (35-39).

Integrated circuit pin control apparatus and method thereof in a data

Growing community of inventors

Austin, TX, United States of America

Linda R Nuckolls