Texas Instruments Corporation

Linda L Hurd

Vaishali Kulkarni

A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. ). A windows-type display ( ) displays sections of computer code ( ), as well as numerical values representing power usage ( ). Next to each section of code, some sort of visual representation of power usage is displayed, such as a bar of a bar graph ( ). Alternatively, the code can be highlighted if power usage exceeds a given threshold, or comments can be provided next to the code for optimizing power usage.

Graphics user interface for power optimization diagnostics

A method of optimizing assembly code of a VLIW processor ( ) or other processor that uses multiple-instruction words ( ), each of which comprise instructions to be executed on different functional units (11 and 11 ) of the processor ( ). The instruction words ( ) are modified, by modifying NOP instructions to minimize bit changes from cycle to cycle in the machine code. Specifically, a NOP is replaced with a proxy NOP, whose syntax is the same as an adjacent instruction but that is treated as a NOP. This modification results in reduced power dissipation.

Power reduction for multiple-instruction-word processors with proxy NOP instructions

A method of optimizing assembly code of a VLIW processor ( ) or other processor that uses multiple-instruction words ( ), each of which comprise instructions to be executed on different functional units ( and ) of the processor ( ). The instruction words ( ) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.

Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words

A method of optimizing assembly code of a VLIW processor (,) or other processor that uses multiple-instruction words (,), each of which comprise instructions to be executed on different functional units (,and,) of the processor (,). The instruction words (,) are modified in accordance with one or more code optimization techniques (FIG.,). Typically, the modifications tend to result in fewer cycle-to-cycle bit changes in the machine code, which results in reduced power consumption.

Power reduction for multiple-instruction-word processors by modification of instruction words

A method for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules. The method involves the steps of, first, providing a set of average current values for each of said modules, for a predetermined plurality of sets of conditions based on predetermined sets of signal line states associated with said module, for each instruction in the instruction set of said processor module, said sets of conditions being selected for dominant power consumption effect on the module. For each module, for each instruction in a block of code to be executed on said processor module, a set of signal line states is generated, associated with said module, for each processor cycle, in sequence. The generated set of signal line states are then tested for said set of conditions. One of said average current values is assigned for each condition so tested that is met. Finally, the running total of said average current values so met is accumulated for each such processor cycle. The average current values can be translated for different frequencies and supply voltages. Also, average current can be converted to average power consumption.

Growing community of inventors

Sugar Land, TX, United States of America

Linda L Hurd