Intel Corporation

Linda L Hurd

Joydeep Ray

Abhishek R Appu

Altug Koker

Dukhwan Kim

Prasoonkumar Surti

John Charles Weast

Mike B Macpherson

Sara S Baghsorkhi

Ben J Ashbaugh

Elmoustapha Ould-Ahmed-Vall

Balaji Vembu

Kamal Sinha

Michael S Strickland

Travis T Schluessler

Liwei Ma

Justin E Gottschlich

Xiaoming Chen

Ping Tak Tang

Narayan Srinivasa

Anbang Yao

Feng Chen

Nadathur Rajagopalan Satish

Farshad Akhbari

Wenyin Fu

Vasanth Ranganathan

Josh B Mastronarde

Subramaniam M Maiyuran

Barath Lakshmanan

Nicolas C Galoppo Von Borries

Tatiana Shpeisman

Chandrasekaran Sakthivel

Sanjeev S Jahagirdar

Eriko Nurvitadhi

Rajkishore Barik

Tsung-Han Lin

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Kevin Nealis

Eric J Hoekstra

Guei-Yuan Lueh

Kiran Chand Veernapu

David M Puffer

Abhishek Venkatesh

Bhushan M Borole

Eric C Samson

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Sherine Abdelhak

Neelay Pandit

Ankur N Shah

Nikos Kaburlasos

Kai Xiao

Atsuo Kuwahara

Aravindh V Anantaraman

Deepak Shashidhar Vembar

Pattabhiraman K

Tomasz Janczak

Supratim Pal

Javier Sebastian Turek

Saurabh Sharma

Brian T Lewis

Slawomir Grajewski

Eric J Asperheim

Jingyi Jin

Lindsey Kuper

Naila Farooqui

Van H Le

Rita H Wouhaybi

Nageen Himayat

Hassnaa Moustafa

Mike MacPherson

Chaitanya Sreerama

Phani Kumar Kandula

Nadine L Dabby

Subhajit Dasgupta

Srikrishnan Venkataraman

Srivallaba Mysore

Daren J Schmidt

Hiroshi Akiba

Gayathri Jeganmohan

Ankitha Chandran

Ahmed Abou-Alfotouh

Johanna M Swan

Min Suet Lim

Xue Yang

Shekoufeh Qawami

Maruti Gupta Hyde

Rajashree Raji Baskaran

Annie Foong

Denica N Larsen

Sherry Chang

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

Multicore processor with each core having independent floating point datapath and integer datapath

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

System for power throttling

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

Concurrent multi-datatype execution within a processing resource

One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

A method of embodiments, as described herein, includes detecting thread groups relating to machine learning associated with one or more processing devices. The method may further include facilitating barrier synchronization of the thread groups across multiple dies such that each thread in a thread group is scheduled across a set of compute elements associated with the multiple dies, where each die represents a processing device of the one or more processing devices, the processing device including a graphics processor.

Barriers and synchronization for machine learning at autonomous machines

One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

Graphics neural network processor, method, and system

An autonomous vehicle is provided that includes one or more processors configured to provide a local compute manager to manage execution of compute workloads associated with the autonomous vehicle. The local compute manager can perform various compute operations, including receiving offload of compute operations from to other compute nodes and offloading compute operations to other compute notes, where the other compute nodes can be other autonomous vehicles. The local compute manager can also facilitate autonomous navigation functionality.

Autonomous vehicle advanced sensing and response

Growing community of inventors

Cool, CA, United States of America

Linda L Hurd