Lucent Technologies Inc.

Lincoln A Fajardo

Sanjay Jinturkar

David Whalley

Jay Patrick Wilshire

Ramesh V Peri

Gang-Ryung Uh

Vincent Phuoc Cao

Yuhong Wang

The invention provides compiler loop optimization techniques to take advantage of a zero overhead loop mechanism (ZOLM) in a processor, e.g., a ZOLM in the form of a zero overhead loop buffer (ZOLB). In an illustrative embodiment, a compiler generates a first set of code, and then applies optimizations to the first set of code so as to generate a second set of code configured to operate efficiently with the ZOLB. The optimizations are designed to increase the number of loops of the first set of code that can be accommodated in the ZOLB, to further reduce the overhead of the loops placed in the ZOLB, and to eliminate redundant loading of the ZOLB. Optimizations for increasing the number of loops that can be accommodated in the ZOLB include, e.g., conditional instructions, loop splitting and function inlining. Optimizations for further reductions in loop overhead include, e.g., loop collapsing and loop interchange. Data flow analysis and loop peeling may be used to avoid redundant loading of the ZOLB.

Compiler optimization techniques for exploiting a zero overhead loop mechanism

A system for debugging the computer program present in read-only memory (ROM) contains a debugger, a processor, read-only memory, a bus and a hardware debugging support module. The hardware debugging support module contains a first register called the range start register, a second register called the range end register and a comparator. The debugger uses a list of &ldquo;n&rdquo; user specified break points to divide a computer program into &ldquo;n&plus;1&rdquo; regions, each of which has a start address and an end address. The first register and the second register of the hardware debugging support module are programmed with the start address and end address of a region which contains a specific address. The comparator is connected to the first register and second register of the hardware debugging support module and is also connected to the bus which connects the read-only memory to the processor. The comparator monitors addresses traveling on the bus and causes the hardware debugging support module to interrupt the processor and transfer control of the computer program to the debugger if a specific address traveling on the bus does not fall within the range defined by the first register and the second register. The debugger then searches the remaining &ldquo;n&plus;1&rdquo; regions to see if the specific address lies within a second region. If such a region is found, then the start address and end address of that second region are entered into the first register and the second register and the computer program is run. However, if such a region is not found, then the computer program has reached a break point and the debugger transfers control of the program to the user. The computer program can then be single stepped to execute the instruction at which the break point was placed to obtain an output address. The start address and end address of the region that contain this output address are programmed into the first register and the second register and the computer program is run. This process is repeated until the entire computer program has been executed.

System for debugging (N) break points by dividing a computer program to (n&plus;1) regions each contains no break point and using two registers to define the start and end addresses of each region

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Kempton, PA, United States of America

Lincoln A Fajardo