Yangtze Memory Technologies Co., Ltd.

Linchun Wu

Wenxi Zhou

Kun Zhang

Zhiliang Xia

Zongliang Huo

Zhong Zhang

Di Wang

Wenyu Hua

Shan Li

ZongLiang Huo

Wei Xie

Cuicui Kong

Bingguo Wang

Yuhui Han

Changzhi Sun

Yaqin Liu

A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.

Semiconductor device including a memory stack and a contact structure in a spacer structure

A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

Three-dimensional memory device and fabrication method for improved yield and reliability

A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

Three-dimensional NAND memory device having word line contact with dielectric filler

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

Memory system, semiconductor device and fabrication method therefor

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Three-dimensional memory devices and methods for forming the same

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

Aspects of the disclosure provide a semiconductor device including a stack structure and a first conductive pillar. The stack structure can include a plurality of interlayer insulating layers and gate layers arranged alternately along a stack direction, and stack structure an array region and a staircase region adjoining the array region. The stack structure has a plurality of staircases in the staircase region arranged corresponding to the gate layers. Each of the gate layers can include a first gate part at the corresponding staircase and a second gate part connected to the first gate part, and a thickness of the first gate part along the stack direction is less than that of the second gate part along the stack direction. The first conductive pillar is arranged in the staircase region and penetrates through the stack structure along the stack direction, and the first conductive pillar is electrically connected with the first gate part.

Semiconductor device and its manufacturing method, memory and memory system

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming a dielectric stack on a substrate, and forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack. The method also includes forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening. The method further includes removing a portion of the first layer located at the bottom of the first opening from a second side of the dielectric stack to expose a portion of the second layer. The method further includes forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.

Method of fabricating three-dimensional NAND memory

Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.

3D NAND memory device with non-uniform channel structure and method for forming the same

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Three-dimensional NAND memory and fabrication method thereof

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Three-dimensional memory devices with supporting structure for staircase region and spacer structure for contact structure and methods for forming the same

A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

Semiconductor devices having a conductive layer stacking with an insulating layer and a spacer structure through the conductive layer

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

Three-dimensional memory device with backside source contact

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

Three-dimensional memory devices

Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.

Growing community of inventors

Wuhan, China

Linchun Wu