Microsoft Technology Licensing, LLC

University of California

Vivante Corporation

Lin Tan

Hao Zhang

Meher P Malakapalli

B Anil Kumar

Madanlal S Musuvathi

Mike M Cai

Frido Garritsen

Timothy Sherwood

Artem Belkine

Eric K Han

Ming Chen

Winston Matthew Penfold Johnston

Meetesh Barua

Pandele Stanescu

Jeroen Dirk Meijer

Meher Prasad Malakapalli

The present invention extends to methods, systems, and computer program products for providing domain, hull, and geometry shaders in a para-virtualized environment. As such, a guest application executing in a child partition is enabled use a programmable GPU pipeline of a physical GPU. A vGPU (executing in the child partition) is presented to the guest application. The vGPU exposes DDIs of a rendering framework. The DDIs enable the guest application to send graphics commands to the vGPU, including commands for utilizing a domain shader, a hull shader, and/or a geometric shader at a physical GPU. A render component (executing within the root partition) receives physical GPU-specific commands from the vGPU, including commands for using the domain shader, the hull shader, and/or the geometric shader. The render component schedules the physical GPU-specific command(s) for execution at the physical GPU.

Para-virtualized domain, hull, and geometry shaders

The present invention extends to methods, systems, and computer program products for para-virtualized GPGPU computation and GDI acceleration. Some embodiments provide a compute shader to a guest application within a para-virtualized environment. A vGPU in a child partition presents compute shader DDIs for performing GPGPU computations to a guest application. A render component in a root partition receives compute shader commands from the vGPU and schedules the commands for execution at the physical GPU. Other embodiments provide GPU-accelerated GDI rendering capabilities to a guest application within a para-virtualized environment. A vGPU in a child partition provides an API for receiving GDI commands, and sends GDI commands and data to a render component in a root partition. The render component schedules the GDI commands on a 3D rendering device. The 3D rendering device executes the GDI commands at the physical GPU using a sharable GDI surface.

Para-virtualized high-performance computing and GDI acceleration

A pattern matching technique for high throughput network processing includes a simple yet powerful special purpose architecture and a set of novel string matching algorithms that can work in unison. The novel set of algorithms allow for bit-level partitioning of rules such that may be more easily implemented in hardware or software. The result is a device that maintains tight worst case bounds on performance, can be updated with new rules without interrupting operation, compiles in seconds instead of hours, and is ten times more efficient than the existing best known solutions in this area.

Pattern matching technique for high throughput network processing

The present invention extends to methods, systems, and computer program products for automatically generating test cases for binary code. Embodiments of the present invention can automatically generate test inputs for systematically covering program execution paths within binary code. By monitoring program execution of the binary code on existing or random test cases, branch predicates on execution paths can be dynamically inferred. These inferred branch predicates can then be used to drive the program along previously unexplored execution paths, enabling the learning of further execution paths. Embodiments of the invention can be used in combination with other analysis and testing techniques to provide better test coverage and expose program errors.

Automatically generating test cases for binary code

A distributed clipping scheme is provided, view frustum culling is distributed in several places in a graphics processing pipeline to simplify hardware implementation and improve performance. In general, many 3D objects are outside viewing frustum. In one embodiment, clipping is performed on these objects with a simple algorithm in the PA module, such as near Z clipping, trivial rejection and trivial acceptance. In one embodiment, the SE and RA modules perform the rest of clipping, such as X, Y and far Z clipping. In one embodiment, the SE module performs clipping by way of computing a initial point of rasterization. In one embodiment, the RA module performs clipping by way of conducting the rendering step of the rasterization process. This approach distributes the complexity in the graphics processing pipeline and makes the design simpler and faster, therefore design complexity, cost and performance may all be improved in hardware implementation.

Method for distributed clipping outside of view volume

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Cupertino, CA, United States of America

Lin Tan