Intel Corporation

Cypress Semiconductor Corporation

Ap Memory Corp, USA

Lin Ma

Wenliang Chen

Kevin X Zhang

Fatih Hamzaoglu

Richard Michael Parent

David G Chapman

Anupam I Arora

Implementations disclosed herein may relate to a memory cell, such as a DRAM memory cell, for example.

Memory cell

A wordline driver circuit can include single stage level shifters to translate a low voltage level (VGND to Vcc) to a high voltage level (Vnwl to Vpp). A wordline driver can further include a two-stage discharge circuit to pull down a wordline from a boosted high voltage Vpp to a boosted low voltage Vnwl. A two-stage discharge circuit can include (i) a first discharge path that can pull the wordline toward a first low voltage VGND; and (ii) a second discharge path that can pull the wordline toward a lower boosted low voltage Vnwl. Initially discharging a wordline to a first low voltage can reduce the amount of charge injected into a boosted low voltage Vnwl supply. A two-stage discharge circuit can be self timed or externally timed.

Dual-voltage wordline drive circuit with two stage discharge

A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

Dynamic multi-Vcc scheme for SRAM cell stability control

An SRAM array is disclosed. The SRAM array includes a plurality of SRAM cells. In one embodiment, the SRAM cells are 6-T SRAM cells that further includes a voltage bias device. The voltage bias device raises the voltage level of a low voltage rail V such that the plurality of SRAM cells are connected to a raised low voltage rail.

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Beaverton, OR, United States of America

Lin Ma