Infineon Technologies Ag

Lin Li

Harald Zweck

Uli Kretzschmar

Varun Kumar

An interconnect connects a first device running a first application and with a first interface and a second device running a second application and with a second interface. The first device has a safety guard which may be used in an operations mode to send safety relevant data from the first application to the second application. Safety information is added to the safety relevant data to create safety marked data. The safety marked data is transmitted to the second application. The safety marked data is also looped back through interconnect to the safety guard which checks the loop back data using the safety information in the loop back data, and when the checking indicates an error, transmits an error notification signal to the first application and/or the second application.

Interconnect bus safety

A traffic anomaly detector of a Peripheral Component Interconnect express (PCIe) system, including filters configured to filter headers of PCIe transaction layer packets (TLPs) based on respective filter criterion; a classifier configured to trigger an event based on one of the filter criterion or a logical combination of a plurality of the filter criteria; an event counter configured to count a number of the events; and a processor configured to detect, based on a value of the event counter, an anomaly in the PCIe TLP traffic.

Anamoly detection system for peripheral component interconnect express

The present disclosure provides a Peripheral Component Interconnect Express (PCIe) controller for a PCIe endpoint device. The PCIe controller includes: a PCIe link interface configured to receive an interrupt request message, wherein the interrupt request message is a message write transaction PCIe transport layer packet (TLP) including an address associated with the PCIe endpoint device and a data value including interrupt information; an interrupt request trigger register configured to receive the data value; a plurality of interrupt lines; and a decode logic circuit connected to the interrupt request trigger register and the plurality of interrupt lines, the decode logic circuit configured to automatically decode a plurality of data bits of the data value when received in the interrupt request trigger register and generate an interrupt signal and provide the interrupt signal on one of the plurality of interrupt lines to an interrupt handling circuit.

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Munich, Germany

Lin Li