Pdf Solutions, Incorporated

Asml Netherlands B.v.

Lin Lee Cheong

Tomonori Honda

Jeffrey Drue David

Richard Gene Burch

Qing Zhu

Michael Keleher

Lakshmikar Kuravi

Yen-Wen Lu

Stefan Hunsche

Yi Zou

Marinus Jochemsen

Bruno M La Fontaine

Chenxi Lin

Jing Su

Dennis Ciplickas

John Kibarian

Brian E Stine

Marc Jurian Kea

Rohan Deodatta Kekatpure

Maxime Philippe Frederic Genin

Wenjin Huang

Yasri Yudhistira

Bogdan Cirlig

Kenneth Harris

Said Akar

Vaishnavi Reddipalli

Methods of identifying a hot spot from a design layout or of predicting whether a pattern in a design layout is defective, using a machine learning model. An example method disclosed herein includes obtaining sets of one or more characteristics of performance of hot spots, respectively, under a plurality of process conditions, respectively, in a device manufacturing process; determining, for each of the process conditions, for each of the hot spots, based on the one or more characteristics under that process condition, whether that hot spot is defective; obtaining a characteristic of each of the process conditions; obtaining a characteristic of each of the hot spots; and training a machine learning model using a training set including the characteristic of one of the process conditions, the characteristic of one of the hot spots, and whether that hot spot is defective under that process condition.

Identification of hot spots or defects by machine learning

A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

Wafer bin map based root cause analysis

Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

Collaborative learning model for semiconductor applications

A robust predictive model. A plurality of different predictive models for a target feature are run, and a comparative analysis provided for each predictive model that meet minimum performance criteria for the target feature. One of the predictive models is selected, either manually or automatically, based on predefined criteria. For semi-automatic selection, a static or dynamic survey is generated for obtaining user preferences for parameters associated with the target feature. The survey results will be used to generate a model that illustrates parameter trade-offs, which will be used to finalize the optimal predictive model for the user.

Rational decision-making tool for semiconductor processes

Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.

Anomalous equipment trace detection and classification

A method including obtaining verified values of a characteristic of a plurality of patterns on a substrate produced by a device manufacturing process; obtaining computed values of the characteristic using a non-probabilistic model; obtaining values of a residue of the non-probabilistic model based on the verified values and the computed values; and obtaining an attribute of a distribution of the residue based on the values of the residue. Also disclosed herein are methods of computing a probability of defects on a substrate produced by the device manufacturing process, and of obtaining an attribute of a distribution of the residue of a non-probabilistic model.

Defect prediction

A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

Maintenance scheduling for semiconductor manufacturing equipment

A method including: determining a value of a characteristic of a patterning process or a product thereof, at a current value of a processing parameter; determining whether a termination criterion is met by the value of the characteristic; if the termination criterion is not met, determining a new value of the processing parameter from the current value of the processing parameter and a prior value of the processing parameter, and setting the current value to the new value and repeating the determining steps; and if the termination criterion is met, providing the current value of the processing parameter as an approximation of a value of the processing parameter at which the characteristic has a target value.

Methods for determining an approximate value of a processing parameter at which a characteristic of the patterning process has a target value

A model is generated for predicting failures at the wafer production level. Input data from sensors is stored as an initial dataset, then data exhibiting excursions or useless impact is removed from the dataset. The dataset is converted into target features, where the target features are useful in predicting whether a wafer will be normal or not. A trade-off between positive and negative results is selected, and a plurality of predictive models are created. The final model is selected based on the trade-off criteria, and deployed.

Failure detection and classsification using sensor data and/or measurement data

A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of 'engineered' features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

Semiconductor yield prediction

Testing data is evaluated by machine learning tools to determine whether to include or exclude chips from further testing.

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San Jose, CA, United States of America

Lin Lee Cheong