Via Technologies, Inc.

Lin-Hung Chen

Chia-Hsing Yu

Jui-Ming Wei

Chien-Ping Chung

Tsung-Yi Lin

A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Memory access system and memory access method thereof

A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for indicating the presence of a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for indicating the presence of a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Bus controller with virtual bridge

A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

Method for determining an operating voltage of floating point error detection

The present invention provides a circuit system for data transmission between LPC devices, comprising: a first LPC bus, connected to a first LPC device; a second LPC bus, connected to a second LPC device; and an LPC host controller, able to drive the first LPC device through the first LPC bus and the second LPC device through the second LPC bus; wherein the LPC host controller further comprises an address register. The present invention further provides a method for data transmission between LPC devices, comprising the steps of: starting a first cycle through a first LPC bus by an LPC host controller, wherein a first LPC device sends a request to have a transaction with a second LPC device, and inserting a plurality of wait states after the request is received by the LPC host controller; and starting a second cycle through a second LPC bus by the LPC host controller, wherein the LPC host controller has a transaction with the second LPC device according to the request from the first LPC device.

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Taipei, Taiwan

Lin-Hung Chen