International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Lin Hu

Hsueh-Chung Chen

Chi-Chun Liu

Brian Joseph Greene

Kafai Lai

Cheng Chi

Jed Walter Pitera

Veeraraghavan S Basker

Daniel J Jaeger

Keith Howard Tabakman

Atsushi Ogino

Kai Zhao

Christopher Nassar

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Source/drain contact depth control

Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

On-chip resistors with direct wiring connections

A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

Design-aware pattern density control in directed self-assembly graphoepitaxy process

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Cohoes, NY, United States of America

Lin Hu