Innogrit Technologies Co., Ltd.

Ati Technologies Inc.

Advanced Micro Devices Corporation

Apple Inc.

Ati Technologies Ulc

Nokia Technologies Oy

Marvell International Limited

Marvellworld Trade Ltd.

S3 Incorporated, Inc.

Nyquist Semiconductor Limited

Lin Chen

Gang Zhao

Wei Jiang

Joseph D Macri

Jie Chen

Ming-Ju Edward Lee

Stephen L Morein

Claude R Gauthier

Qun Zhao

Zining Wu

Steven Morein

Shawn Chen

Shiann-Ming Liou

Brad W Simeral

Albert Wang

Bo Fu

Mark A Yoshimoto

Jamie L Langlinais

Paul Aurelio Martinez

Scott D Morrison

Curtis C Mead

Cheng-Yun Hsu

Sam Huynh

Giancarlo F De La Cruz

Ming Lu

Yan Chen

Gin S Yee

Arvind Bomdica

Tao Wei

Daniel Vaquero

Dong-Ying Kuo

Yongjiang Wang

Wyeman Chen

Sagheer Ahmad

Randy X Zhao

Zhengtian Feng

Vu Thanh Vo

Roger Niu

Kangmin Hu

Yanwen Bai

Siji Menokki Kandiyil

Joe Macri

Shu-Shia Chow

Zhou Hong

Edward Lee

Basavaraja Shanthappa Vandrotti

Abhilash Mathew

Hiok-Tiaq Ng

John Ling

Jennifer Ho

Poornachandra Rao

Jeremy Alves

Chiahung Chien

Satya Vadlamani

Hongsen Yu

Sindhu Rajaram

Siji MK

Gin Yee

Systems, apparatus and methods are provided for selecting a performance profile for a storage system. A method may include: generating a set of performance profiles for a non-volatile storage system, performing a thermal calibration by running a first test under a first performance profile and a second test under a second performance profile, obtaining a first maximum temperature under the first performance profile and a second maximum temperature under the second performance profile, selecting an optimal performance profile from the set of performance profiles based on comparing the first maximum temperature and the second maximum temperature to a predetermined threshold value and operating the non-volatile storage system under the optimal performance profile. Each of the set of performance profiles may include settings for hardware components of the non-volatile storage system.

Adaptive thermal calibration for throttling prevention

Systems and apparatus are provided for power management of non-volatile storage (NVM) systems. A storage controller includes a command queue and a processor. The processor is configured to, in response to a data transfer rate from a host falling below a predetermined threshold and the command queue containing no command, enter a pseudo-idle power state by turning off input and output (IO) drivers of a memory interface coupling the storage controller and a non-volatile memory device and keeping on an internal memory of the storage controller.

System and method for power management in solid state storage systems

Disclosed is a non-volatile memory and a system having a controller and two non-volatile memories. The two non-volatile memories are configured to communicate with the controller through a same channel, and to send respective status information thereof to the controller through a same line. The first non-volatile memory is configured to: determine whether the line is available for sending the status information; upon determining that the line is available, send an alert to the controller using a processor by driving the line to a first logic level for a first duration and stopping driving the line upon expiration of the first duration; upon expiration of the first duration, determine a logic level of the line; upon determining that the logic level of the line is a second logic level, send its status information to the controller through the line upon expiration of a second duration.

Non-volatile memory with an arbitration function on shared status channel

Disclosed herein are systems, methods and devices for controlling output of a storage device during read operations. The method comprises: measuring a length of a temporal gap between first and second consecutive read bursts from a storage device, the first and second read burst are in response to first and second read commands received by the storage device, respectively; generating a state code according to the length, wherein the state code has a first value when the length is zero, a second value when the length is equal to or shorter than a threshold time length but is non-zero, and a third value when the length is greater than the threshold time length; and controlling output of the storage device according to the state code.

Systems, methods and devices for reading a memory of a storage device

Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.

Systems and methods for power and thermal management in a solid state drive

Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.

Partial logical-to-physical (L2P) address translation table for multiple namespaces

A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.

Hybrid PCB topology and layout with clamshell placement for storage applications

Systems, apparatus and methods are provided for power management of non-volatile storage (NVM) systems. A non-volatile storage system may include a first interface to be coupled to a host, a NVM device, a storage controller including a command queue and a processor, and a second interface coupling the storage controller and the NVM device. The processor may be configured to handle data transfer requests from the host in an active power state, monitor the command queue and a data transfer rate on the first interface, determine that the data transfer rate falls below a predetermined threshold and the command queue is empty, enter a pseudo-idle power state, determine that there is a new command from the host, and exit the pseudo-idle power state and enter the active power state.

Systems, apparatus and methods are provided for performing cache program operations in a non-volatile storage system. A method may comprise issuing a first cache program operation from a storage controller to a non-volatile storage device to write data to a first regular block, writing the data to the first regular block and a copy of the data to a backup block, determining that a program error has occurred while writing the data to the first regular block, asserting the program error to the storage controller, retrieving a mapping between the first regular block and the backup block, issuing a read operation to read the copy of the data from the backup block, reading the copy of the data from the backup block and issuing a second cache program operation to write the data to a second regular block and marking the first regular block as defective.

Cache program with backup blocks

Systems, apparatus and methods are provided for managing a removable solid state storage system for data loss prevention. A method may include maintaining a standby mode for a timer of the removable solid state storage system until the removable solid state storage system is disconnected from an external power supply, setting an operation time interval on the timer, using the timer to count how long the removable solid state storage system has been disconnected, sending an interrupt to a storage controller of the removable solid state storage system from the timer when the timer counts to the operation time Interval, and performing data loss prevention operations using a power supplied by a removable battery.

Solid state storage system with data loss prevention and user alert

Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.

Temperature assisted NAND flash management

Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

System and method for managing solid state storage devices in low temperature environment

Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

Robustness-aware NAND flash management

Systems, apparatus and methods are provided for electrical mirroring implemented by a storage controller in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a plurality of non-volatile storage devices and a storage controller. The storage controller may be configured to perform an electrical mirroring configuration process comprising: determining a system topology of the non-volatile storage system and which targets are in mirrored non-volatile storage devices and setting respective register bits in the storage controller for all targets in all mirrored non-volatile storage devices of the plurality of non-volatile storage devices.

Electrical mirroring by NAND flash controller

Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Command based on-die termination for high-speed NAND interface

Growing community of inventors

Cupertino, CA, United States of America

Lin Chen