Juniper Networks, Inc.

Alpha & Omega Semiconductor Corporation

Alpha and Omega Semiconductor (cayman) Ltd.

Alpha and Omega Semiconductor International LP

Texas Instruments Corporation

Active-semi, Inc.

Innogrit Technologies Co., Ltd.

Lin Chen

Xiaosong Yang

Changming Liu

Kuang Ming Chang

Qihong Huang

Zhiqiang Niu

Wei-Chung Wu

Ning Sun

Yuan Gu

Ziwei Yu

Madhur Bobde

Wei Jiang

Yueh-Se Ho

Yan Xun Xue

Steven Huynh

Xiaobin Wang

Jun Yang

Long-Ching Wang

Matthew Alan Grant

Jonathan S Brodsky

Yan Ke

Jian Yin

Ye Zhao

Dening Wang

Kae Ann Wong

Wenliang Chen

Gregory M Lebovitz

Shawn Chen

Tao Zhao

Tzu-Hsin Lu

Sitthipong Angkititraku

ChengYuan He

Apparatus and associated methods relate to a Source Terminal Replication Compensation Circuit for simulating an accurate fraction of a load current. In an illustrative example, a Source Terminal Replication Compensation Circuit (STRCC) may be connected to a motor driving circuit. The STRCC, for example, may include a simulation transistor configured to have a simulated structure of a main transistor in a motor driving circuit. The STRCC may include, for example, a disturbance rejection module (DRM). The DRM may be connected to a source terminal of the sense transistor, and a source terminal of the main transistor. When the DRM is connected to a current sensing resistor, a sense current is generated as a predetermined fraction of a load current of the motor driving circuit, wherein the predetermined fraction is less than 1%. Various embodiments may advantageously reduce heat dissipations at the current sensor resistor.

SENSEFET for motor control

A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Power converter for high power density applications

Power converter for high power density

A memory system is disclosed in the present disclosure. The memory system may include at least one first type of memory configured on at least one first rank and to operate at a first frequency, and at least one second type of memory configured on at least one second rank and to operate at a second frequency. The memory system may also include a physical block (PHY) configured to generate a first clock at the first frequency and a second clock at the second frequency.

Multi-frequency memory interface and methods for configurating the same

A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a 'drain 1, drain 2, drain 1, and drain 2' pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Common source land grid array package

A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

HV converter with reduced EMI

A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding current to turn off the synchronous rectifier and to start the next switching cycle. At this point, the voltage across the primary switch has been discharged and the primary switch can be turned on with zero drain-to-source voltage. In other embodiments, zero voltage switching for the off-transition of the primary switch is realized by coupling a capacitor across the primary switch or by coupling a capacitor across the primary winding, or both.

Forced zero voltage switching flyback converter

A device may receive a request to access a resource. The resource may be associated with resource information. The device may obtain rating information based on receiving the request. The rating information may identify a rating associated with the resource. The device may apply an access rule based on the rating information. The access rule may identify an access indicator to generate based on the rating information. The access indicator may indicate an action to perform related to the resource. The device may generate the access indicator based on applying the access rule to the rating information. The device may store, locally in one or more memories, information that indicates an association between the access indicator and the resource information.

Internet address filtering based on a local database

Zero voltage switching flyback converter for primary switch turn-off transitions

A backup device detects that a session timer associated with a session in a session table of the backup network device has expired and ages out the session from the session table based on whether a first message has been sent to a master network device regarding the session and whether a second message has been received from the master network device regarding the session.

Solving timeout issues in backup devices

Techniques are described for managing failover in redundant network devices. In particular, each device in a set of redundant network devices includes redundant processing modules. Each module provides a separate operating environment for a set of network services. Each network device includes a control unit that receives configuration information that specifies individual weight values for each of the modules and a threshold value for the network device. The control unit detects failures of the modules and transfers primary responsibility for performing the network service to a second network device when the threshold value is exceeded by a weighted sum of the weight values for the failed modules.

Configurable redundant security device failover

A system protects database operations performed on a shared resource. The system may chunk memory to form a set of memory chunks which have memory blocks, at least some of the memory blocks including database objects. The system may configure at least one binary search tree using the memory chunks as nodes and buffer a set of pointers corresponding to the memory blocks. The system may further validate the buffered pointers and dereference validated buffered pointers.

Protection of database operations

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San Jose, CA, United States of America

Lin Chen