International Business Machines Corporation

Limor Plotkin

Ofer Geva

Yaniv Maroz

Shiran Raz

Haining S Yang

Robert C Wong

Noam Jungmann

Elazar Kachir

Amira Rozenfeld

Omer Heymann

Udi Nir

Dana Bar-Niv

Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.

Circuit generation based on zero wire load assertions

A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.

Estimating timing convergence using assertion comparisons

A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.

Boost cell supply write assist

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Yehuda, Israel

Limor Plotkin