Texas Instruments Corporation

Other

Novatek Microelectronics Corp.

Liming Xiu

Kairos Microsystems Corporation

Zhihong You

Hugh Thomas Mair

Karl H Renner

Haydar Bilhan

Gonggui Xu

Walter Heinrich Demmer

Po-Chin Hu

Shawn Anthony Fahrenbruch

Jason Meiners

Xiaopeng Li

Steven Derrick Clynes

Hongbing Lian

Christopher Sean Tracy

Ming-Chieh Lin

Daniel Xavier Dudek

Wen Li

Grady Cook

Yihe Hu

A TAF-DPS based circuits and methods to improve electronic system's frequency accuracy and enhance its frequency stability is disclosed in this application. Present invention creates a circuit architecture and a calculation scheme for compensating frequency source's frequency error. Present invention further discloses a method of incorporating said scheme into functional chip built in either ASIC or FPGA fashion. Present invention further presents a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance from the time synchronization perspective.

Method and apparatus for improving frequency source frequency accuracy and frequency stability

An interface adapter for facilitating the data communication among computation modules in a Network-on-Chip SoC comprises 1) a FIFO block having certain number of storage cells for temporarily storing the data to be transported between two communicating modules; 2) a TAF-DPS clock generator and a multi-phase generator attached at the FIFO write side for generating the write clock for FIFO and the driving clock for the transmitter, a TAF-DPS clock generator and a multi-phase generator attached at the FIFO read side for generating the read clock for FIFO and the driving clock for the receiver; 3) a write pointer controller and a read pointer controller for reading the FIFO status and controlling the TAF-DPS clock generators at the write side and at the read side, respectively. A design scheme of using said interface adapters in Network-on-Chip SoC design includes a plurality of computation modules, routing modules, said interface adapters, a network of communication link, a network of global clock distribution. Methods of creating the interface adapter and using it in the Network-on-Chip SoC design are also disclosed.

Circuits and methods of TAF-DPS based interface adapter for heterogeneously clocked Network-on-Chip system

Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input. Methods of creating flexible clock signal to drive application comprise: 1) selecting one or more strategic areas in said programmable logic chip; 2) creating one or more TAF-DPS clock generator for each said area by using the configurable resource in said area; 3) creating control function to control the frequency and duty-cycle of the TAF-DPS clock generator output, said control function can be circuit created from configuring configurable blocks, said control function can also be achieved by software; 4) driving the circuits in application by the flexible clock generated from said TAF-DPS clock generator.

Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same

Circuits for distributing a global clock signal to all clock sinks on a chip for synchronous operation comprises 1) a plurality of synchronous clock areas (SCA), each SCA having a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) clock source for generating a function clock, said TAF-DPS clock source has frequency synthesis and phase adjustment capabilities on its output of function clock; 2) a network for distributing a low frequency global clock signal to said plurality of synchronous clock areas, said global clock signal is used as reference for said TAF-DPS clock sources in all SCAs; 3) a plurality of clock sinks in each SCA, said clock sinks are driven by said function clock generated from said TAF-DPS clock source. Methods of distributing a low frequency global clock signal to all clock sinks in a chip for synchronous operation are also disclosed.

Circuits and methods of TAF-DPS based chip level global clock signal distribution

Circuits for measuring TOF between two electrical signals comprises 1) a slow TAF-DPS clock signal generator for generating a slow clock signal, a fast TAF-DPS clock signal generator for generating a fast clock signal, said slow TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer, said fast TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer; 2) a phase detector for receiving said slow and fast clock signals and detecting point-of-coincidence between said slow and fast clock signals; 3) a first digital counter driven by said slow clock signal for storing the number of slow clock cycles and a second digital counter driven by said fast clock signal for storing the number of fast clock cycles; 4) a calibrator for calibrating said gate ring oscillators; 5) a calculation block for calculating TOF measurement result. Methods of using a slow TAF-DPS clock generator and a fast TAF-DPS clock generator for measuring TOF between two electrical signals are also disclosed.

Circuits and methods of TAF-DPS vernier caliper for time-of-flight measurement

A microelectronic system comprises at least one circuit block that performs certain signal processing functions and at least one clock generation circuit that produces at least one Time-Average-Frequency clock signal which comprises clock pulses of at least two different lengths. The said lengths are measured in time. The arithmetic mean of the lengths of all the pulses that exist in a time frame of one second is calculated. The Time-Average-Frequency clock pulse train is made in such way that the arithmetic inversion of the said arithmetic mean equals to a predetermined value that is the clock frequency of the Time-Average-Frequency clock signal. At least one said circuit block in the said microelectronic system is driven by the said Time-Average-Frequency clock signal. The said circuit block is setup-constrained using the minimum pulse length found among the lengths of all the pulses in the Time-Average-Frequency clock signal.

Microelectronic system using time-average-frequency clock signal as its timekeeper

One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Frequency synthesizer and frequency synthesizing method for converting frequency's spurious tones into noise

An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides. A method of creating such adaptive clock generation circuit is also presented.

Circuit and method for adaptive clock generation using dynamic-time-average-frequency

A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

Circuits and methods for time-average frequency based clock data recovery

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (f) and the destination frequency (f). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

Circuits and methods for using a flying-adder synthesizer as a fractional frequency divider

A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.

Circuits and methods for one-wire communication bus of using pulse-edge for clock and pulse-duty-cycle for data

A Time-Average-Frequency direct period synthesizer is used to improve crystal-less frequency generator's frequency stability. It includes (a) a temperature sensor circuit to compensate temperature-induced frequency instability; (b) a voltage sensor circuit to compensate voltage-induced frequency instability; (c) a calibration circuit to correct manufacture-related frequency error; (d) a frequency control word update circuit to receive the temperature- and voltage-related frequency adjustments, and the calibration-related adjustment, to generate the corresponding frequency control word in a predetermined schedule; (f) a Time-Average-Frequency direct period synthesizer to receive said frequency control word in the predetermined schedule and produce a clock signal with a frequency that is stable and accurate by counteracting the frequency variation caused by crystal-less oscillators' temperature and voltage dependence and correcting the frequency error introduced in manufacture process. Methods of correcting crystal-less oscillators' frequency error and compensating its frequency variation are also disclosed.

Circuit and method of using time-average-frequency direct period syntheszier for improving crystal-less frequency generator frequency stability

A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Method of reducing water-wave noise and system thereof

A phase locked loop including a flying-adder divider circuit configured to receive phases of a periodic signal from a frequency generator and output a feedback signal to a phase detector, and a method of generating a periodic signal using such a flying-adder circuit, are disclosed. The flying-adder divider circuit generally includes a flying-adder and one or two divide-by-N dividers. The flying-adder receives K phases of the periodic signal, where K is an integer of at least 2, and generates a divided periodic signal from the K phases. The phase locked loop may include flying-adder divider circuits inside and/or outside the loop.

Circuits and methods for clock generation using a flying-adder divider inside and optionally outside a phase locked loop

A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked.

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Plano, TX, United States of America

Liming Xiu