Cadence Design Systems, Inc.

Limin He

Jing Yang Chen

So-Zen Yao

Liang-Jih Chao

Wenyong Deng

Jimmy Kwok-Ching Lam

Jianmin Li

Mark Steven Hahn

Stefanus Mantik

Soohong A Kim

Chris Morrison

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Routing interconnect of integrated circuit designs with varying grid densities

Interconnect routing methods of integrated circuit designs

Routing interconnect of integrated circuit designs

An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation

Routing methods for integrated circuit designs

Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Computationally efficient design rule checking for circuit interconnect routing design

Method and apparatus for scalable interconnect solution

An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions can provide an efficient method of determining how much slack, if any, is present in the timing of a design.

System and method for generating and using stage-based constraints for timing-driven design

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Saratoga, CA, United States of America

Limin He