Texas Instruments Corporation

Lily Springer

Joe R Trogolo

Jeff D Smith

Jozef C Mitros

David Leonard Larkin

Dhaval Atul Saraiya

Ashish V Gokhale

Makoto Takemura

Binghua Hu

Chin-Yu Tsai

Sheldon Douglas Haynie

Wen-Hwa M Chu

Sameer P Pendharkar

Imran Khan

Tathagata Chatterjee

Andy Strachan

Kentaro Takahashi

Jeffrey P Smith

Hiroshi Yamasaki

He Lin

Dening Wang

Roland Bucksch

Shaibal Barua

Toshiyuki Tani

Gang Xue

Robert Graham Shaw

James Garrett Homack

Haim Horovitz

Paul C Mannas

Kun Chen

Tathagata Chatterlee

Chao Wu

Josef Czeslaw Mitros

A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.

Contact array optimization for ESD devices

A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.

Vertical ESD protection device

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or). The integrated high voltage capacitor further includes capacitance uniformity structures () located at least partially within the insulator () and a second capacitor plate () located over the insulator ().

Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor

A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.

Verification method with the implementation of well voltage pseudo diodes

Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Versatile system for optimizing current gain in bipolar transistor structures

Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.

Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout

A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Single poly-emitter PNP using dwell diffusion in a BiCMOS technology

A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

Memory device with reduced cell size

Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology

A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps

An electronic device architecture is described comprising a field effect device in an active region of a substrate . Channel stop implant regions and are used as isolation structures and are spaced apart from the active region by extension zones and . The spacing is established by using an inner mask layer and an outer mask layer to define the isolation structures.

Field effect transistor with improved isolation structures

An EEPROM ( ) comprises a source region ( ), a drain region ( ); and a polysilicon layer ( ). The polysilicon layer ( ) comprises a floating gate comprising at least one polysilicon finger ( A- E) operatively coupling the source region ( ) and drain region ( ) and a control gate comprising at least one of the polysilicon fingers ( A- E) capacitively coupled to the floating gate. The EEPROM ( ) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Single poly EEPROM with reduced area

Growing community of inventors

Dallas, TX, United States of America

Lily Springer