Intel Corporation

Other

Lily Pao Looi

Manoj Khare

Akhilesh Kumar

Kai Cheng

Sin Sim Tan

Stephan Jourdan

Faye A Briggs

Kenneth C Creta

Selim Bilgin

Mahesh U Wagh

Ravi Rajwar

Srikanth T Srinivasan

Jeffrey Charles Swanson

Sivakumar Radhakrishnan

Suresh S Chittor

Tuan M Quach

Bryan L Spry

Robert A Mayer

Mohan J Kumar

Efraim Rotem

Eliezer Weissmann

Doron Rajwan

Robert J Greiner

James A Sutton, Ii

Nadav Shulman

Mikal Hunsaker

Ioannis T Schoinas

James B Crossland

Robert J Royer, Jr

Shivnandan D Kaushik

Dean A Mulla

Su Wei Lim

Ashish Gupta

Michael W Leddige

Robert T George

Zvika Greenfield

Rupin H Vakharwala

Anant S Deval

Chia-Hung Sophia Kuo

Shaun M Conrad

Nitin Y Borkar

Ronald W Swartz

Dorit Shapira

Dale J Juenemann

Esfir Natanzon

Vui Yong Liew

Michel P Cekleov

Rohit R Verma

Keith Robert Pflederer

James A Boyd

Aimee D Wood

Liqun Cheng

Jeff Van Tran

Yi-Feng Liu

Suvansh Krishan Kapur

John A Urbanski

David R Jackson

Rajee S Ram

Marcus W Song

Ken Creta

Bart Plackle

Frank Verhoorn

Prashanth Nimmala

Christopher Van Beek

Gary C Chow

James A Beavens

Stanley Steven Kulick

Stephan J Jourdan

In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

System, apparatus and method for controlling a processor based on effective stress information

A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

Fast page fault handling process implemented on persistent memory

Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

Power control techniques for integrated PCIe controllers

Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

Throttling integrated link

Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

Device power management state transition latency advertisement for faster boot time

Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express&#x2122; (PCIe&#x2122;) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe&#x2122; format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

Method, apparatus and system for single-ended communication of transaction layer packets

To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.

Method, apparatus, and system for enabling platform power states

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Integrating intellectual property (IP) blocks into a processor

Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.

Integration of processor and input/output hub

Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.

Dynamic and idle power reduction sequence using recombinant clock and power gating

A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

Power measurement techniques of a system-on-chip (SOC)

A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

Method and apparatus for reducing memory latency in a cache coherent multi-node architecture

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Portland, OR, United States of America

Lily Pao Looi