Carsem (m) Sdn. Bhd.

Carsem Semiconductor Sdn. Bhd.

Lily Khor

Yong Lam Wai

Phuah Kian Keung

Lau Choong Keong

Oo Choo Yee

Boon Pek Liew

Thong Kai Choh

King Hoo Ong

Yan Shan Ng

Edmund Sales Cabatbat

Kai Choh Thong

Au Keng Yeun

Lynn Simporios Guirit

Ho Tuck Ming

Ong King Hoo

A package is disclosed. The package includes a leadframe, and a first die, attached to the leadframe. The package also includes first bond wires, each attached to one of the first bond pads of the first die and to one of the leads of the leadframe, and a package body molded over each of a portion of the die pad of the leadframe, a portion of the leads of the leadframe, a first portion of the first die, and one or more of the first bond wires. The molded package body defines a cavity, and a second portion of the first die contacts neither of the die pad and the package body. The package also includes a second die having second bond pads, where the second die is attached to the first die. The package also includes second bond wires, each attached to the first and second die.

Molded integrated circuit packages and methods of forming the same

An electronic package is formed by placing a semiconductor die within an opening in a leadframe and performing a first molding operation. The die is wirebonded to the leadframe and a final encapsulation is performed with a second molding operation.

Low-profile electronic package

A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.

Pre-molded integrated circuit packages

A stacked electronic package includes a substrate and conductive straps each having sides, a top, and a bottom opposite the top. Each conductive strap is coupled along the bottom to an upper surface of the substrate and is separate from others of the conductive straps. A length of at least one of the sides is greater than a width of at least another one of the sides. An encapsulant extends over the upper surface and side surfaces of the substrate and the sides of the conductive straps. A passive electronic component is disposed over the conductive straps, and each conductive strap is coupled along the top to a terminal of the passive electronic component.

Stacked electronic packages

A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.

Color yield of white LEDs

A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.

Wafer level package using stud bump coated with solder

A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface, prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads, curing the curable material and dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer.

Method of manufacturing a cavity package

There is disclosed a flip-chip-type method of assembling semiconductor devices. A one-step encapsulation process promotes adhesion of the die to the lead fingers and prevents the potential of shorts developing between the adjacent bumps or lead fingers. Conventional mold compound is used to reduce localized stress caused by coefficient of thermal expansion (CTE) mismatch between the die and substrate, or the lead frame.

Flip chip on lead frame

There is disclosed a flip-chip-type method of assembling semiconductor devices. The proposed invention offer one step encapsulation process to promote adhesion of die to the lead finger and prevent the potential of shorts from developing between the adjacent bumps ( ) or lead fingers. Conventional mold compound ( ) is used to reduce localized stress causes by coefficient of thermal expansion (CTE) mismatch between the die ( ) and substrate, or the lead frame ( ). This is particularly favorable in promoting greater mechanical robustness of the semiconductor devices. With one step encapsulation process proposed by the present invention, manufacturing process is made simpler, faster and relatively cheaper.

Growing community of inventors

Ipoh, Malaysia

Lily Khor