International Business Machines Corporation

Lily Jielu Zhang

Daniel Mark Dreps

Andreas H A Arp

Jason Lee Frankel

Chad Andrew Marquart

Douglas J Malone

Franklin M Baez

Ching Lung Tong

A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

Growing community of inventors

Wappingers Falls, NY, United States of America

Lily Jielu Zhang