International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Rensselaer Polytechnic Institute

Lili Cheng

Chih-Chao Yang

Ashim Dutta

Robert J Fox, Iii

Sanford Chu

Luke G England

Roderick Alan Augur

Robert Fox

David Paul Brunco

Dina H Triyoso

Amir H Hirsa

Michael J Vogel

Bernard A Malouin, Jr

Jeasung Park

Joseph D Olles

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.

Tall bottom electrode structure in embedded magnetoresistive random-access memory

A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.

Stepped contact within memory region

A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.

Contact structure formation for memory devices

Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

Metal-insulator-metal capacitors including nanofibers

Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

High-density metal-insulator-metal capacitors

Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime

An oscillating liquid lens and imaging system and method employing the lens are provided. The liquid lens includes a substrate with a channel opening extending through the substrate. A liquid drop is disposed within the channel and is sized with a first droplet portion, including a first capillary surface, protruding away from a first substrate surface, and a second droplet portion, including a second capillary surface, protruding away from a second substrate surface. The liquid lens further includes an enclosure at least partially surrounding the substrate, and including a chamber. The liquid drop resides within the chamber, and the liquid lens includes a second liquid disposed within the chamber in direct or indirect contact with the liquid drop, and the liquid lens further includes a driver for oscillating the liquid drop within the channel.

Growing community of inventors

Rexford, NY, United States of America

Lili Cheng