University of California

Transphorm Inc.

Transphorm Technology, Inc.

Likun Shen

Umesh Kumar Mishra

Primit A Parikh

Ilan Ben-Yaacov

Arpan Chakraborty

Robert Coffie

Yifeng Wu

Rongming Chu

David Michael Rhodes

Ronald Avrom Barr

Sten Heikman

Rakesh K Lal

Tomas Apostol Palacios

Carl Joseph Neufeld

Lee McCarthy

Kurt Vernon Smith

James Leroy McKay

Rakesh Lai

An electronic component includes at least three terminals extending from a component package. The component includes a depletion-mode III-N transistor, and an enhancement-mode transistor in the package. A gate electrode of the enhancement-mode transistor is electrically connected to the first terminal, a source electrode of the enhancement-mode transistor and a gate electrode of the depletion-mode III-N transistor are electrically connected to the second terminal, a drain electrode of the enhancement-mode transistor is electrically connected to a source electrode of the depletion-mode III-N transistor, and a drain electrode of the depletion-mode III-N transistor is electrically connected to the third terminal. The drain electrode includes multiple drain pads each sequentially a further distance from the third terminal, where a wire-bond extends from each drain pad to the third terminal, each wire-bond having a length, where a diameter of the longest wire-bond is greater than the diameter of the shortest wire-bond.

III-N devices with improved reliability

Techniques for improving reliability of III-N devices include holding the III-N devices at a first temperature less than or equal to 30&#xb0; for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the III-N devices and a first drain-source voltage greater than 0.2 times a break down voltage of the III-N devices; and holding the III-N devices at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than a threshold voltage of the III-N devices and a second drain-source voltage greater than 0.2 times a breakdown voltage of the III-N devices. After holding the III-N devices at the first and second temperatures, screening the III-N devices based on electrical performance of one or more parameters of the III-N devices.

Conditions for burn-in of high power semiconductors

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Enhancement mode III-N HEMTs

The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Interdigitated multiple pixel arrays of light-emitting devices

An electrolysis transistor for providing high-density electrochemistry and products utilizing the same, and high-efficiency electrolysis and electrochemical processes is disclosed. The electrolysis transistor may comprise an electrolyte, one or more working electrodes for transferring charge to or from said electrolyte, and one or more gate structures for altering electrode over-voltage and modifying the barrier at the electrode-electrolyte interface, reducing the voltage necessary for electrolysis. An electrochemical or photo-electrochemical cell may incorporate one or more of these electrolysis transistors.

Electrolysis transistor

Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Semiconductor heterostructure diodes

The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Growing community of inventors

Goleta, CA, United States of America

Likun Shen