Oracle International Corporation

Sun Microsystems, Inc.

Lik Cheng

Gregory Frederick Grohoski

Heechoul Park

Clement Fang

David Jeffrey

Neil Duncan

Venkatesh P Gopinath

Raymond A Heald

Paul J Dickinson

Hua-Yu Su

Wen-Jay Hsu

Shih-Huey Wu

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Detection of multiple accesses to a row address of a dynamic memory within a refresh period

A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC. The applied leakage stress is adjusted to establish a desired pass/fail threshold and to detect other process variations or defects so that the sense amplifier can be applied to detect the voltage differential during a read operation. The applied leakage stress can also be applied to write driver circuitry such that a write driver along with the applied stress provide enough voltage level to screen difficult-to-write cell from a easy-to-write cell during a write operation. The plurality of stress inducing signals are controlled such that the appropriate leakage stress may be applied to force a leakage to Vdd or Vss associated with the cell through the complementary data lines.

Scheme for screening weak memory cell

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San Jose, CA, United States of America

Lik Cheng