Integrated Device Technology, Inc.

Halo Microelectronics International

Lijie Zhao

Rui Liu

Gustavo James Mehas

Zhitong Guo

Tae Kwang Park

Tao Qi

Siqiang Fan

Yue Wang

Hai Tao

Stephen Ulbrich

Kien Chan Vi

Jeffrey G Barrow

Zhao Fang

Jianbin Hao

Suming Lai

Song Gao

Kenneth Chung-Yin Kwok

Zhuyan Shao

Qinghua Yue

Quinghua Hubert Yue

Gao Song

An apparatus includes a first drain/source region and a second drain/source region surrounded by an isolation ring formed over a substrate, the isolation ring formed being configured to be floating, and a first diode connected between the substrate and the isolation ring, wherein the first diode is a Schottky diode.

Latch-up free high voltage device

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N&#x2212;K)th capacitor, and a constant binary weight from the (N&#x2212;K)th capacitor to a (N&#x2212;K&#x2212;2+2)th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

ADC apparatus and control method

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2steps, each of which has a value equal to an integer multiplying 2of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2number of N-bit digital signals based on the at least 2steps of the digitally controlled offset voltage, summing the at least the 2number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

In accordance with aspects of the present invention, a method and apparatus for demodulating an amplitude-modulated wireless power signal is presented. A method of receiving an amplitude modulated component of a wireless power transmission signal according to some embodiments includes receiving an input signal, wherein the input signal is based on an amplitude modulated wireless power signal; and applying an offset to the input signal to receive the amplitude modulated component. A demodulator according to some embodiments can include a first voltage-to-current converter that receives an input signal related to an amplitude modulated wireless power signal; a second voltage-to-current converter that receives an offset signal; and a summing node that adjusts a first current produced by the first voltage-to-current converter by a second current produced by the second voltage-to-current converter to produce an output signal.

Recovery of modulation amplitude in wireless charger tx demodulation

According to another embodiment, a system includes a driver circuit that drives a first output and a second output; a coil coupled between the first output and the second output such that the driver circuit drives current through the coil in response to control signals; and a programmable slew circuit coupled to the driver circuit. In some embodiments, a switch is coupled between the first output and the coil. In some embodiments an over-voltage protection circuit is coupled to protect the driver circuit.

Circuits and systems for low power magnetic secure transmission

In accordance with aspects of the present invention, a wireless power circuit is presented. In some embodiments, the wireless power circuit includes one or more high-side transistors; one or more low-side transistors coupled in series with the one or more high-side transistors, wherein the one or more low-side transistors can be controlled as current sources.

Wireless receiver rectifier low side current limited operation

In some embodiments, a wireless power charging circuit includes a wireless power receiver configured to receive wireless power from a receive coil and to produce a first voltage; an open loop capacitor divider coupled to receive the first voltage from the wireless power receiver and configured to provide a second voltage, the second voltage being reduced from the first voltage; and a linear battery charger coupled to receive the second voltage from the open loop capacitor and configured to provide a charging voltage to provide to a battery coupled to the system.

High efficiency wireless charger system

A method of adaptively operating a transmit detection circuit is presented. The method includes powering the transmit detection circuit with a capacitor charged by an LDO; receiving a digital ping signal from a transmitter; receiving a clock signal from a local oscillator; updating a register to accommodate timing of the digital ping signal; and generating a signal indicating whether the transmitter is present.

Adaptive transmitter present detection

A power converter control circuit includes a first ramp generator connected to an input voltage and configured to produce a first ramp signal; a second ramp generator connected to the input voltage and configured to produce a second ramp signal; an error amplifier configured to produce an error amplifier output. The first ramp signal and the error amplifier output are used to produce a first (pulse width modulation) PWM signal and the second ramp signal and the error amplifier output are used to produce a second PWM signal. The first and second PWM signals control an operating state of the circuit. In some embodiments, the first ramp signal includes an extended ramp reset time. In some embodiments, the first ramp generator includes a switching device, a current source, and a capacitor.

Multiple-level buck boost converter control

In accordance with aspects of the present invention, a magnetic secured transmission system is presented. A magnetic secure transmission (MST) system can include a full-bridge driver that includes four transistors configured to regulate current through a coil; and a driving controller coupled to drive the full-bridge driver at a high frequency. In some embodiments, the transistors in the full bridge regulator are driven with a high frequency pulsed-wave modulated (PWM) signal to control the current through the coil. A method of magnetic secured transmission (MST) of MST data according to some embodiments includes receiving the MST data; generating coil data in response to the MST data; driving transistors in a full bridge at a high frequency to drive current through a coil according to the coil data.

Low power magnetic secure transmission system

A charging system that includes a switching control circuit coupled to four series-coupled MOSFET transistors; a flying capacitor coupled across two of the four series-coupled MOSFET transistors; and node between the two of the four series coupled transistors that couples to an output inductor to form a buck regulator is presented. Embodiments of the charging system can have increased efficiency, can reduce the size and inductance of the output inductor, and can be produced with a low voltage process.

Battery charging system

A rectifier circuit can include a plurality of FETs arranged as a rectifier; and a start-up circuit applied to each of the plurality of FETs that turn each of the FETs off during a circuit startup period, wherein the start-up circuit provides a large impedance for low power dissipation during normal operation of the rectifier.

Growing community of inventors

San Jose, CA, United States of America

Lijie Zhao