International Business Machines Corporation

Lijiang L Wang

Douglas Wayne Kemerer

Edward W Seibert

Gustavo Enrique Tellez

Daniel Nelson Maynard

Mark Steven Styduhar

Jeanne P S Bickford

Anand Kumaraswamy

Terry M Lowe

Peter S Wissell

In one embodiment, at least one design library element having a design marker shape is applied to a yield checking tool having library element types, each having a yield checking deck threshold and a marker shape. The design marker shape is compared to each of the marker shapes. A determination is made as to whether the design library element satisfies the yield checking deck threshold associated with the library element type having a matching marker shape. In another embodiment, a product design formed from a design library elements each having a design marker shape is applied to the yield checking tool in a similar manner. In instances where the design library elements do not satisfy the yield checking deck threshold, then the design library element is updated by modifying the design library elements, placement of the design library elements in the product design, and/or wiring connecting the design library elements.

Yield optimization for design library elements at library element level or at product level

A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.

Identifying parasitic diode(s) in an integrated circuit physical design

A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).

Method and system for improving integrated circuit manufacturing productivity

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South Burlington, VT, United States of America

Lijiang L Wang