Intel Corporation

Lihu Rappoport

Ronny Ronen

Adi Yoaz

Franck Sala

Zeev Sperber

Sreenivas Subramoney

Ron Gabor

Stanislav Shwartsman

Jared Warner Stark, Iv

Jayesh Gaur

Stephan Jourdan

Robert S Chappell

Ido Ouziel

Oded Lempel

Chen Koren

Adarsh Chauhan

Jason W Brandt

Michael Mishaeli

Ronak Singhal

Bob Valentine

Joseph Nuzman

Igor Yanover

George Leifman

Ilhyun Kim

Mattan Erez

Pavel I Kryukov

Stephan J Jourdan

Kamil Garifullin

Lior Libis

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Bret L Toll

Christopher J Hughes

Jesus Corbal

Hong Wang

Edward Thomas Grochowski

Stephen H Gunther

Ohad Falik

David B Papworth

Sergiu D Ghetie

Deepak K Gupta

Anant V Nori

Rodrigo Branco

Hisham Shafi

Thomas R Huff

James D Allen

Scott P Bobholz

Michael Bekerman

Buford M Guy

Wojciech S Powiertowski

Gregory Pribush

Sagar V Dalvi

Ariel Sabba

Jared W Stark

Scott J Cape

Nir Tell

Seyed Yahya Sotoudeh

Yulia Kurolap

Sumeet Bandishte

Pankaj Raghuvanshi

Yair Berger

Gilad Holzstein

Mohan J Kumar

Alexander Gendler

Shlomo Raikin

Saurabh Gupta

Ganapati Srinivasa

Ahmad Yasin

Theodros Yigzaw

Alexandre J Farcy

Ofer Levy

Jose Andy Vargas

Julius Yuli Mandelblat

Larisa Novakovsky

Adrian C Moga

Israel Diamand

Geeyarpuram N Santhanakrishnan

Ibrahim Hur

Nicolas I Kacevas

Niranjan K Soundararajan

Ragavendra Natarajan

Alex Gerber

Niranjan Soundararajan

Lev Makovsky

Michael Tal

Andrey Kluchnikov

Robert L Hinton

Hanna Alam

Alexey Sivtsov

Prathmesh Kallurkar

Amir Leibovitz

Yoav Almog

Jeffrey Baxter

Swaraj Sha

Choon Wei Khor

Stephen J Jourdan

Pooja Roy

Alexandr Titov

Gil Shmueli

Adrian Flesler

An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

Region aware delta prefetcher

Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.

Device, method, and system to facilitate improved bandwidth of a branch prediction unit

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

Code prefetch instruction

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

De-prioritizing speculative code lines in on-chip caches

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

Technology for dynamically tuning processor features

Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

Detecting a dynamic control flow re-convergence point for conditional branches in hardware

A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Accelerating memory fault resolution by performing fast re-fetching

A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.

Instruction length decoder system and method

In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.

System, apparatus and method for context-based override of history-based branch predictions

Growing community of inventors

Haifa, Israel

Lihu Rappoport