Boe Technology Group Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Liheng Wei

Lingtong Li

Huijuan Yang

Xiaoqing Shu

Maoying Liao

Yi Zhang

Tingliang Liu

Peng Xu

Tianci Chen

Yixuan Long

Nanhao Chen

Bo Zhang

Yang Zhou

Lu Bai

Song Liu

Lianbin Liu

Junxiu Dai

Rendong Li

A display substrate and a display device are provided, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes a pixel circuit, a scan drive circuit, a control drive circuit and a buffer drive circuit; the pixel circuit includes a node reset transistor, a writing transistor, a reset signal line connected to a control electrode of the node reset transistor, a scan signal line connected to a control electrode of the writing transistor, and a control signal line; reset signal lines of pixel circuits of first to K-th rows are electrically connected with the buffer drive circuit, reset signal lines of pixel circuits of (K+1)-th to N-th row are electrically connected with the scan drive circuit or the control drive circuit.

Display substrate and display device

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y>Z.

Pixel circuit, method of driving pixel circuit, display panel, and display device

The disclosure provides a shift register including: input circuit configured to write signal from signal input terminal to third node in response to signal from first clock signal terminal; first control circuit configured to write voltage from first power terminal into first node in response to signals from preset control signal terminal and preset clock signal terminal; second control circuit configured to write voltage from second power terminal to first node in response to signal from signal input terminal; and output circuit configured to write voltage from second power terminal to signal output terminal in response to voltage at first node, and to write voltage from first power terminal to signal output terminal in response to voltage at fourth node. Third node is coupled to fourth node. The present disclosure further provides a gate driving circuit and a display apparatus.

Shift register, gate driving circuit and display apparatus

A shift register is configured to be applied to a display substrate including a plurality of rows of sub-pixels. The shift register is electrically connected to a single row of sub-pixels, and is further configured to transmit a scan signal and a reset signal to the single row of sub-pixels. The shift register includes a scan circuit and a reset circuit. The scan circuit is configured to output the scan signal due to cooperation of a first input signal, a first clock signal, a second clock signal, a first voltage signal and a second voltage signal. The reset circuit is configured to output the reset circuit due to cooperation of a second input signal, a third clock signal, a fourth clock signal, a third voltage signal and a fourth voltage signal. The scan circuit and the reset circuit are configured to output signals independently from each other.

Shift register having scan cicuit and reset circuit, scan driving circuit and display substrate

Disclosed are a display substrate and a display device. The display substrate includes a pixel circuit and a scan drive circuit, wherein the pixel circuit includes a write transistor and a scan signal line, the scan signal line is electrically connected with a control electrode of the write transistor, and the scan drive circuit includes a first scan clock signal line and a second scan clock signal line. A signal of the first scan clock signal line is a first clock signal, a signal of the second scan clock signal line is a second clock signal, and both of the first clock signal and the second clock signal are periodic clock signals. A duration of the first clock signal being a low-level signal in one period is different from a duration of the second clock signal being a low-level signal in one period.

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y≥Z.

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Beijing, China

Liheng Wei