Nanjing Semidrive Technology Ltd.

Lihang Zhang

Jun Xie

Qiang Zhang

Shaohui Gong

Yujing Qiu

Qiaoyu Ye

Xiongfei Liu

A multi-chip interconnection system includes a plurality of chips. A chip of the plurality of chips includes an extend serial peripheral interface (XSPI) master terminal, a data transmission terminal, an XSPI slave terminal, and a data reception terminal. The XSPI master terminal includes an advanced extensible interface (AXI) slave interface. The data transmission terminal accesses the AXI slave interface via an AXI bus. The XSPI slave terminal includes an AXI master interface. The data reception terminal accesses the AXI master interface via the AXI bus. An XSPI master terminal of a chip is connected to an XSPI slave terminal of another chip via an XSPI bus. The XSPI master terminal of the chip performs encoding on AXI information of the data transmission terminal of the chip received via the AXI bus and transmits encoded AXI information to the XSPI slave terminal of the another chip via the XSPI bus.

Multi-chip interconnection system and method thereof

An error correction code circuit includes a first error correction code circuit configured to generate correction data and a first correction check bit according to received source data and a source check bit corresponding to the received source data, a second error correction code circuit connected to the first error correction code circuit, and configured to, according to the correction data and at least one of the first correction check bit or the source check bit, determine whether the correction data is wrong and generate a second correction check bit, and a comparison circuit connected between the first error correction code circuit and the second error correction code circuit, and configured to compare the first correction check bit with the second correction check bit and determine whether the first correction check bit is wrong.

Error correction code circuit and error correction method

A dynamic loading system of an off-chip non-volatile memory based on virtual mapping includes the off-chip non-volatile memory, an on-chip memory, an on-chip mapping device, a memory access controller, and an off-chip memory. The on-chip mapping device is configured to construct a mapping relationship between a logical partition and a physical partition of the on-chip memory. The memory access controller is configured to parse a memory access of a system into an access to the logical partition, configure a prediction algorithm of data loading, and send a memory loading request to the off-chip memory loading device. The off-chip memory loading device is configured to construct a mapping relationship between a program partition of the off-chip non-volatile memory and the physical partition of the on-chip memory.

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Nanjing, China

Lihang Zhang