Peking University

Chengdu Huawei Symantec Technologies Co., Ltd.

Huawei Technologies Co., Limited

Yunding Network Technology (beijing) Co., Ltd.

Metis IP (suzhou) LLC

Huawei Digital Technologies Co., Ltd.

Lifeng Liu

Jinfeng Kang

Yi Wang

Tao Li

Yang Xin

Min Huang

Xiaoyan Liu

Bin Gao

Bing Chen

Huasheng Liu

Hao Tang

Zhibin Zheng

Feifei Zhang

Peng Huang

Guoliang Li

Wenfeng Li

Dong Zhang

Kai Zhao

Pu Liu

Shi Wan

Bing Jiang Sun

Yuchen Wang

Jian Meng

Qi Yi

Yuhu Zhang

Yulin Feng

Yi Hou

Sheng Yao

Dedong Han

Hongliang Zhu

Jiaming Pan

Huazhang Ma

Zhiwei Ye

Wenhao Lu

Canjin Gao

Liu Tan

Yizhou Zhang

Dai Zheng

Guanzhou Lin

Yixian Yang

Yuhua Cheng

Hongyan Feng

Michael Ko

Yuansha Chen

The present disclosure relates to methods and systems for managing and controlling resources. A system for managing and controlling resources may comprise a storage device configured to store a set of instructions, one or more processors configured to communicate with the storage device. When executing the set of instructions, the one or more processors may be configured to cause the system to collect resource usage data through one or more meters, process the resource usage data based on a preset algorithm to determine resource usage state, and control at least the one or more meters and/or one or more smart devices to perform specified operations based on the resource usage state. The present disclosure provides methods and systems for managing and controlling resources based on meters or smart devices controlled by the network.

Resource management and control method and system

The present disclosure relates to a method and system for controlling a smart device. The method includes obtaining correlating information of the smart device. The correlating information includes at least one of smart device information or a communication status of the smart device. The method includes determining indication information of the smart device by processing the correlating information of the smart device according to a preset algorithm. The method includes performing designated operations related to the smart device based at least in part on the indication information.

Methods and systems for controlling an intelligent device

An operating circuit and an operating method of a resistive random-access memory are provided, the operating circuit includes: at least one capacitance connected in series with the resistive random-access memory, so that the resistive random-access memory is grounded through the at least one capacitance. The operating method includes: connecting at least one capacitance in series with a resistive random-access memory, so that the resistive random-access memory is grounded through the capacitance; applying a forming pulse voltage or a set pulse voltage on the resistive random-access memory to achieve a forming operation or a set operation of the resistive random-access memory.

Operating circuit and operating method of resistive random access memory

The present disclosure relates to a method and system for controlling a smart device. The method may include obtaining correlating information of the smart device. The correlating information may include at least one of smart device information or a communication status of the smart device. The method may include determining indication information of the smart device by processing the correlating information of the smart device according to a preset algorithm. The method may include performing designated operations related to the smart device based at least in part on the indication information.

The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

Data search systems and methods

The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

Multi-bit full adder based on resistive-switching devices and operation methods thereof

Embodiments of the present invention disclose a method, an apparatus, and a system for establishing an FCoE communication connection and a name server. According to a WWN world wide name identifier of a target to be accessed, a destination MAC address used to access the target to be accessed is acquired. According to the destination MAC address, a login operation is performed for the target to be accessed, to establish an FCoE fiber channel over Ethernet communication connection, so that an FCoE initiator may directly establish a communication connection with an FCoE target, thereby reducing data transmission delay and lightening the processing load of an original FCoE forwarder.

Method, apparatus, name server and system for establishing FCOE communication connection

A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time tby using parameters obtained from the fitting. The data retention time of the RRAM device may be predicted by combining voltage acceleration and temperature acceleration.

Method for measuring data retention characteristic of resistive random access memory device

A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element. Using the scheme of the above embodiments, the durability characteristic of the resistive switching device can be improved, such as degradation of high-low resistance value window and the failure of the device with transition times can be reduced.

Resistive switching memory device and method for operating the same

A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

Resistive random access memory device, method for manufacturing the same, and method for operating the same

A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element () and a Schottky diode (). The Schottky diode () and the resistive-switching element () are connected in series. The Schottky diode () includes a metal layer and a semiconductor layer contacting each other. An interface between the metal layer and the semiconductor layer has a non-planar shape.

Resistive-switching device capable of implementing multiary addition operation and method for multiary addition operation

The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by '1' successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to '0' with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by &#x2018;1&#x2019; with a set pulse being applied thereto. In this way, multiary addition operation is implemented.

A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

Three-layered neuron devices for neural network with reset voltage pulse

A method, a system, and an apparatus for establishing communication are disclosed. The method is invented to establish communication between at least two communication parties including a first communication party and a second communication party. The method includes: sending a Cryptographically Generated Address (CGA) request to the first communication party; receiving CGA parameters and a CGA signature returned by the first communication party; and authenticating the CGA parameters and the CGA signature, and establishing communication with the first communication party if the authentication succeeds. By using the method disclosed herein, in the process of establishing communication, the communication party authenticates the CGA parameters and CGA signature carried in the CGA extension header to determine authenticity of the CGA, thus preventing the IP address spoofing and preventing or mitigating the network security problems caused by the IP address spoofing.

Method, system and apparatus for establishing communication

Growing community of inventors

Beijing, China

Lifeng Liu