Micron Technology Incorporated

Other

Battelle Energy Alliance, LLC

Lodestar Licensing Group LLC

Macron Technology, Inc.

Lifang Xu

Indra V Chary

Shuangqiang Luo

Scott D Schellhammer

John David Hopkins

Paolo Tessariol

Jian Li

Nancy M Lomeli

Thomas Gehrke

Zaiyuan Ren

Matthew J King

Harsh Narendrakumar Jain

Jivaan Kishore Jhothiraman

Scott E Sills

Haitao Liu

Jordan D Greenlee

Michael J Bernhardt

Anton J De Villiers

Shan Ming Mou

Martin F Schubert

Justin B Dorhout

Rita J Klein

Everett Allen McTeer

Vladimir Odnoblyudov

Xiao Li

Bo Zhao

Gurtej S Sandhu

Sanh D Tang

Akira Goda

Kamal M Karda

John Mark Meldrim

Richard J Hill

Kunal Shrotri

Adam L Olson

Christopher J Larsen

Yi Hu

Suresh Ramarajan

Merri Lyn Carlson

Gowrisankar Damarla

Sri Sai Sivakumar Vegunta

Rithu K Bhonsle

Kar Wui Thong

John B Matovu

Rutuparna Narulkar

David S Meyaard

Shashank Saraf

Kevin R Gast

David H Wells

Roger W Lindsay

Anilkumar Chandolu

Collin Howder

Aaron R Wilson

Brett D Lowe

Lars P Heineck

Daniel Billingsley

Matthew Park

Umberto Maria Meotto

Vinayak Shamanna

Prakash Rau Mokhna Rau

Xiaosong Zhang

Sidhartha Gupta

Rohit Kothari

David Daycock

Jason Reece

Xiaolong Fang

Lingyu Kong

Joel D Peterson

Sok Han Wong

Michael J Gossman

Tingkai Li

Eldon Nelson

Yoshiaki Fukuzumi

George Matamis

Graham Richard Wolstenholme

David A Kewley

Alyssa N Scarbrough

Emilio Camerlenghi

Ming Zhang

Erik R Byers

Damir Fazil

Dimitrios Pavlopoulos

M Jared Barclay

Shruthi Kumara Vadivel

Biow Hiem Ong

Martin Jared Barclay

Tien Minh Quan Tran

Mohadeseh Asadolahi Baboli

Kah Sing Chooi

Zhen Feng Yow

Shicong Wang

Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.

Memory circuitry comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells

A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Methods of forming microelectronic devices including differently sized conductive contact structures

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases includes steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

Microelectronic devices with different staircased stadiums having consistent multi-tier step riser height, and related systems and methods

An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Apparatuses including interconnect structures including dielectric material surrounded by conductive material, and related memory devices

A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.

Microelectronic devices, and related electronic systems and methods

Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

Textured optoelectronic devices and associated methods of manufacture

A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Microelectronic devices comprising stack structures having pillars and elliptical conductive contacts

Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

Staircase formation in a memory array

Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Microelectronic devices with a polysilicon structure above a staircase structure, and related methods

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Driver placement in memories having stacked memory arrays

Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods

A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Methods of forming microelectronic devices

Microelectronic devices including differently sized conductive contact structures, and related memory devices, electronic systems, and methods

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Boise, ID, United States of America

Lifang Xu