Texas Instruments Corporation

Lieyi Fang

Feng Ying

Haydar Bilhan

Charles M Branch

Gonggui Xu

Ramesh Chandrasekaran

Cetin Kaya

Lars Risbo

James Robert Hochschild

Erkan Bilhan

Kuok Y Ling

Jason Meiners

Daramana G Gata

Claus Niels Neesgaard

James Teng

Gary Lee

Yong Han

Jeff Berwick

Asit Shankar

Shifeng Zhao

A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

Over-current detection for a power field-effect transistor (FET)

The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)() with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product K*Iindependent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump ().

High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth

A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit () includes a clamping capacitor () that couples to an automatic clamping circuit portion () to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (V) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion () connects to the customizable clamping circuit portion () to clamp any portion of the video input signal to a second predetermined reference voltage (V) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer () connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Clamping circuit with wide input dynamic range for video or other AC coupled signals

An image processing apparatus () for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the offset and optical black correction circuit is programmable. The present invention includes a first circuit () to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler () coupled to a first programmable gain amplifier (). An adder () connects between the first programmable gain amplifier () and a second gain amplifier () for adding in the optical black offset to the optical black signal input from the CCD. A second circuit () includes a reverse programmable gain amplifier () connected to the output of the second programmable gain amplifier () to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier (). The second circuit () also includes an integrator () coupled to the reverse programmable gain amplifier () to integrate the difference between the incoming signal and the desired optical black value. The second circuit () couples to the adder () to add the positive and negative difference to the optical black signal. An analog-to-digital converter () converts the sampled signal for further processing at the output of the image processing apparatus ().

Analog optical black clamping circuit for a charge coupled device having wide programmable gain range

A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit ( and ) for receiving an input signal and a symmetry circuits ( and ) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (I ) provides current to a common node (N ) in which current is advantageously steered to each half circuit ( and ) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Delay circuit with current steering output symmetry and supply voltage insensitivity

A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.

Low jitter ring oscillator architecture

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Plano, TX, United States of America

Lieyi Fang