Realtek Semiconductor Inc.

Aiconnx Technology Corporation

Lien-Hsiang Sung

Hsu-Jung Tung

Wei-Liang Cheng

Yu-Pin Lin

Yi-Shu Chang

Pui-Kei Leong

Wun-Lin Chang

Tzu-Min Yeh

Shan-Yuan Yang

An audio control device and a method of controlling a multi-channel sound system are provided. The audio control device is configured to control the audio output of a multimedia device which includes a first and a second sound receiving devices. The audio control device includes an audio output port and a control circuit which performs the following steps: (A) controlling a test signal to be outputted from the audio output port at a first time point; (B) receiving a first input signal generated by the first sound receiving device, and recording a second time point; (C) receiving a second input signal generated by the second sound receiving device, and recording a third time point; and (D) calculating a speaker position according to the first time point, the second time point, the third time point, and a distance between the first sound receiving device and the second sound receiving device.

Audio control device and method of controlling multi-channel sound system

An electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit transmits the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiver. The audio timing unit generates an internal reference signal adjusts a frequency of the internal reference signal according to a receiving speed of the audio data, and generates the CTS according to the internal reference signal and the pixel clock signal so that the receiver can generate an audio clock signal for playing the audio data according to the pixel clock signal and the CTS.

Electronic device and method for transmitting video data and audio data

A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.

Chip, layout design system, and layout design method

A multimedia audio/video system includes a multimedia audio/video transmitting end and a multimedia audio/video receiving end. The multimedia audio/video transmitting end includes a multimedia data generator and a first data converter. The multimedia data generator is used to generate a multimedia data conforming to a first transmission protocol. The first data converter is used to convert the multimedia data conforming to the first transmission protocol into a multimedia data conforming to a second transmission protocol. The multimedia audio/video receiving end includes a second data converter which is used to convert the multimedia data conforming to the second transmission protocol into the multimedia data conforming to the first transmission protocol. The multimedia data conforming to the first transmission protocol is transmitted via multiple cables, while the multimedia data conforming to the second transmission protocol is transmitted via a single cable.

Multimedia audio/video system

A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.

Signal transmission system, transmitter encoding apparatus and receiver decoding apparatus

A method for identifying and pairing a signal transmitting device, including: obtaining a setting value of a master identification key; obtaining a setting value of a slave identification key; determining whether at least one of the setting values equals to an initial value; determining whether the setting value of the master identification key equals to the setting value of the slave identification key when none of the setting values equals to the initial value; and controlling the signal processing device to operate in a limited mode when the setting value of the master identification key and the setting value of the slave identification key are not equal. In the limited mode, a signal processing device does not output any signal to the signal transmitting device or ignores any signal received from a signal transmitting device, or the signal processing device only outputs a limited signal to the signal transmitting device.

Signal processing system and method for identifying and pairing a signal transmitting device

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.

Integrated circuit self-repair method and integrated circuit thereof

A signal processing system includes a signal processing device including a processor and a memory device storing first information and a signal transmitting device including a memory device storing second information. The processor reads the memory devices to obtain the first information and the second information, determines a threshold date according to a first date indicated by the first information and a margin, and determines whether a second date indicated by the second information is earlier than the threshold date. When the second date is earlier than the threshold date, the processor controls the signal processing device to operate in a limited mode. In the limited mode, the signal processing device does not output any signal to the signal transmitting device or ignores any signal from the signal transmitting device, or the signal processing device only outputs a limited signal to the signal transmitting device.

The electronic device with power-off partition includes a signal transmitting module, two repeater modules, and a working module. Each of the repeater modules includes a first power domain, a second power domain, and a transceiver circuit. A transmission path between the first power domain and the second power domain is maintained at a logic state when the second power domain is in power off mode. The transceiver circuit of one of the two repeater modules encodes a standby signal obtained from the signal transmitting module and transmits an encoded standby signal. The transceiver circuit of the other of the repeater modules decodes the encoded standby signal and transmits a decoded standby signal. The working module transmits, according to the decoded standby signal, a power-off signal to the transceiver circuits of the two repeater modules, so that the second power domains enter the power-off mode in response to the power-off signal.

Electronic device with power-off partition and partition-based power-off method therefor

A split-type display system includes a processing device, a display device, and a transmission cable connecting the devices. The processing device includes a processing unit and a low-to-high unit. The processing unit generates a first image signal having both a first transmission rate and a first channel number. The low-to-high unit converts the first image signal into a second image signal having both a second transmission rate and a second channel number. The first transmission rate is lower than the second transmission rate. The display device includes a high-to-low unit and a display unit. The high-to-low unit receives and converts the second image signal into a third image signal having both a third transmission rate and a third channel number. The display unit displays the third image signal. a number of channels of the transmission cable is the same as the second channel number.

Split-type display system

A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words.

A control signal transmission circuit and a control signal receiving circuit for an audio/video interface are provided. The control signal transmission circuit includes an audio/video interface encoder, a signal packaging circuit and a data allocator. The audio/video interface encoder is configured to receive an audio packet and supports a user-defined packet format. The signal packaging circuit is configured to receive a first control signal and package the first control signal into a control data packet according to the user-defined packet format. The data allocator is configured to receive a video data and a second control signal and to mix the second control signal and the video data to generate a mixed data packet. The audio/video interface encoder packages the control data packet, the mixed data packet and the audio packet according to an audio/video transmission protocol to generate an audio/video and control data.

Control signal transmission circuit and control signal receiving circuit for audio/video interface

A video transmission system includes a first processing circuit and a second processing circuit. The first processing circuit is configured to output a composite video signal. The composite video signal includes a video area, an extension area, and an edge area. The extension area stores a non-video signal. The second processing circuit is configured to receive the composite video signal and extract the non-video signal from the composite video signal.

Video transmission system

A split-type display system includes a processing device, a display device, and a transmission cable connecting the processing device and the displaying device. The processing device includes a processing unit, a first and a second conversion unit. The display device includes a third and a fourth conversion unit, and a display unit. The processing unit generates a first image signal and a first timing control signal. The first and the second conversion units, respectively, converts the first image signal and the first timing control signal into a second image signal and a second timing control signal. The third and the fourth conversion units, respectively, receive and convert the second image signal and the second timing control signal into a third image signal and a third timing control signal. The display unit displays the third image signal according to the third timing control signal.

An integrated circuit and a signal transmission method thereof are provided. The integrated circuit includes a first power domain, a second power domain, and a weakly pull circuit. The first power domain is powered by a first power source, the second power domain is powered by a second power source, and the second power domain transmits a signal to the first power domain through a transmission path. The weakly pull circuit is signally connected to the transmission path. When the second power domain is in a power-off mode, the weakly pull circuit maintains the transmission path stably at a logic level to prevent unknown signals from entering the first power domain from the second power domain and disturbing the normal operation of the first power domain.

Growing community of inventors

Hsinchu, Taiwan

Lien-Hsiang Sung