International Business Machines Corporation

Lidor Goren

Alex Raphayevich

Omer Heymann

Moshe Leibowitz

Ronit Bustin

Gil Noy

Maya Speiser

Niv Amit

David Michael Fried

Ishtiaq Ahsan

Jiun-Hsin Liao

Tamara Aviv

A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.

Post silicide testing for replacement high-k metal gate technologies

A parameterized cell library including variable names corresponding to characteristics of components on an integrated circuit design may reference variable values stored in a first rule layer via internally used rule names stored in a second rule layer. The first and second rule layers may be stored as association tables. The first rule layer may store rule names corresponding to one or more geometric constraints of the integrated circuit design, and the rule names may directly reference variable values derived from a technology manual. The second rule layer may store internally used rule names corresponding to rule names stored in the first rule layer, and the internally used rule names may reference the rule names stored in the first rule layer.

Method for creating a parameterized cell library dual-layered rule system for rapid technology migration

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Method and system for enhancing circuit design process

The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects ('WMO') may be inserted into the wiring routing on a 'WMO-per-segment' basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {'C'; one &#x201c;RC&#x201d; arrangement; 'n' times &#x201c;&#x3a0;&#x201d;-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

Method and system for modeling wiring routing in a circuit design

The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects ('WMOs') for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

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Netanya, Israel

Lidor Goren