Intel Corporation

Tahoe Research, Ltd.

Lidong Xu

Yi-Jen Chiu

Wenhao Zhang

Yu Han

Zhipin Deng

Xiaoxia Cai

Hong Jiang

James M Holland

Chen Wang

Abhishek R Appu

Altug Koker

Subramaniam M Maiyuran

Jill MacDonald Boyce

Vasanth Ranganathan

Nikos Kaburlasos

Ya-Ti Peng

Ke Chen

Srinivasan Embar Raghukrishnan

Dmitry E Ryzhov

Pieter Kapsenberg

Prasoonkumar Surti

Adam T Lake

Satya N Yedidi

Guei-Yuan Lueh

Iole Moccagatta

Huan Dou

Joydeep Ray

Christopher J Hughes

Sanjeev S Jahagirdar

Michael Apodaca

Scott R Janus

Xinmin Tian

Brent E Insko

Zhijun Lei

Durgaprasad Bilagi

Jason Daniel Tanner

Changliang Wang

Sang-Hee Lee

Sang-hee Lee

Jong Dae Oh

Atthar H Mohammed

Fangwen Fu

Hiu-Fai R Chan

Naveen Matam

Heon-Mo Koo

Yi-Chen Chiu

An apparatus for super resolution imaging includes a convolutional neural network () to receive a low resolution frame () and generate a high resolution illuminance component frame. The apparatus also includes a hardware scaler () to receive the low resolution frame () and generate a second high resolution chrominance component frame. The apparatus further includes a combiner () to combine the high resolution illuminance component frame and the high resolution chrominance component frame to generate a high resolution frame ().

Super resolution using convolutional neural network

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

A method for image content classification is described herein. The method includes counting a number of distinct color numbers in an image. The method also includes clustering blocks with a same distinct color number into a same class and determining a block occupancy rate of each color number for the image. Finally, the method includes classifying the image according to the block occupancy rate via a plurality of classifiers communicatively coupled in series.

Image content classification

Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. In an example encoder, first circuitry is to encode video input data into a bitstream according to a bitstream syntax, wherein the video input data includes one or more pictures, the one or more pictures are partitioned into one or more coding tree blocks, the one or more coding tree blocks are partitioned into slices including one or more coding tree blocks, the one or more coding tree blocks include one or more transform blocks according to a transform tree including a split_transform_flag indicative of the split of a given coding block into corresponding one or more transform blocks, the split_transform_flag is coded using CABAC, and a context index associated with the CABAC coding of the split_transform_flag is based on a value. Second circuitry of the encoder is to output the bitstream.

Size based transform unit context derivation

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Data locality enhancement for graphics processing units

Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.

Face augmentation in video

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Systems and methods for error detection and control for embedded memory and compute elements

An example apparatus for enhancing video includes a decoder to decode a received 360-degree projection format video bitstream to generate a decoded 360-degree projection format video. The apparatus also includes a viewport generator to generate a viewport from the decoded 360-degree projection format video. The apparatus further includes a convolutional neural network (CNN)-based filter to remove an artifact from the viewport to generate an enhanced image. The apparatus further includes a displayer to send the enhanced image to a display.

Enhancing 360-degree video using convolutional neural network (CNN)-based filter

Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.

Sub-pictures and sub-picture sets with level derivation

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Graphics processing unit processing and caching improvements

Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Methods and systems for motion vector derivation at a video decoder

An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

Modular motion estimation engine for tree-based video

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

Growing community of inventors

Beijing, China

Lidong Xu