Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Intel Corporation

Lidia Warnes

Michael Bozich Calhoun

Dennis Carr

Teddy Lee

Ricardo Ernesto Espinoza-Ibarra

Melvin K Benedict

Durgesh Srivastava

Francesc Guim Bernat

Mark A Schmisseur

Andrew Christopher Walton

Dan Vu

Bassam N Coury

Rasika Subramanian

Sujoy Sen

Mark Edward Shaw

Thomas E Willis

Hugh Wilkinson

Michael F Fallon

Patrick Schoeller

Francois Dugast

Douglas Carrigan

Rita H Wouhaybi

Matthew James Adiletta

Karthik Kumar

Thomas Willhalm

Gregg Bernard Lesartre

Debra Bernstein

Blaine Douglas Gaither

William Ralph Wheeler

Siamak Tavallaei

Russ William Herrell

Alaa R Alameldeen

Larry Jay Thayer

Zhe Wang

Muthukumar Swaminathan

Eric L Pope

Chris Michael Brueggen

Erin Antony Handgen

Martin Goldstein

Donald L Faw

Andy M Rudoff

Hau Jiun Chen

Ananthan Ayyasamy

Christian Petersen

Dheemanth Nagaraj

Aline C Kenfack Sadate

Aaron R Mandle

Chris Petersen

Patricia M Mwove Shaffer

Florent Pirou

Ankit Patel

Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.

Memory access tracing

Methods and apparatus to minimize hot/cold page detection overhead on running workloads. A page meta data structure is populated with meta data associated with memory pages in one or more far memory tier. In conjunction with one or more processes accessing memory pages to perform workloads, the page meta data structure is updated to reflect accesses to the memory pages. The page meta data is used to determine which pages are 'hot' pages and which pages are “cold” pages, wherein hot pages are memory pages with relatively higher access frequencies and cold pages are memory pages with relatively lower access frequencies. Variations on the approach including filtering meta data updates on pages in memory regions of interest and applying a filter(s) to trigger meta data updates based on (a) condition(s). A callback function may also be triggered to be executed synchronously with memory page accesses.

Method to minimize hot/cold page detection overhead on running workloads

Examples described herein relate to providing an interface to an operating system (OS) to create different memory pool classes to allocate to one or more processes and allocate a memory pool class with a process of the one or more processes. In some examples, a memory pool class of the different memory pool classes defines a mixture of memory devices in at least one memory pool available for access by the one or more processes. In some examples, memory devices are associated with multiple memory pool classes to provide multiple different categories of memory resource capabilities.

Memory pool management

Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both. Near memory cache management includes current data location tracking, access counting and other caching heuristics, eviction of data from near memory cache to pool memory and movement of data from pool memory to memory cache.

Memory thin provisioning using memory pools

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

Ballooning for multi-tiered pooled memory

A system for generating a robustness score for hardware components, nodes, and clusters of nodes in a computing infrastructure is provided. The system includes a memory and at least one processing device coupled to the memory. The processing device is to obtain first telemetry data associated with a selected portion of a computing infrastructure, and the selected portion includes a first node and a first hardware component. The processing device is further to obtain first metadata associated with the selected portion, input one or more telemetry inputs corresponding to the first telemetry data into a machine learning model, input one or more metadata inputs corresponding to the first metadata into the machine learning model, and generate, from the machine learning model, a first robustness score for the first hardware component representing a health state of the first hardware component.

Creating robustness scores for selected portions of a computing infrastructure

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.

Tenant based allocation for pooled memory

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

Error counters on a memory device

Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

Validation of a repair to a selected row of data

In one example in accordance with the present disclosure, a system for partial backup during runtime includes a memory module having a volatile memory and a non-volatile memory. The system also includes a backup controller. The backup controller determines that a backup should occur in the memory module. The backup controller determines a backup domain of the volatile memory. The backup controller causes a deactivation domain of the volatile memory to be deactivated, where the deactivation domain includes the backup domain. The backup controller causes the backup to initiate during normal runtime of the system. The backup includes data in the backup domain of the volatile memory being saved to the non-volatile memory.

Partial backup during runtime for memory modules with volatile memory and non-volatile memory

Examples provide systems and a method for handling errors during run-time back up of volatile memory. The method includes initiating a backup of a volatile memory domain to a non-volatile memory domain. Memory registers are polled for completion of the backup. It is determined if the backup was successful. If not successful, an operating system (OS) is notified that the backup failed, and the backup is completed to an alternate media.

Handling errors during run time backups

Example implementations relate to generating statuses for data images. In example implementations, an event, in response to which a save operation is initiated on a memory module, may be identified. A data image may be generated during the save operation. A status may be generated for the generated data mage. The status may include an event portion indicative of the identified event, and a completion portion indicative of whether the save operation was completed.

Status for generated data image

The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

Dynamically composable computing system, a data center, and method for dynamically composing a computing system

Growing community of inventors

Roseville, CA, United States of America

Lidia Warnes