Marvell Israel (misl) Ltd.

Marvell Asia Pte., Ltd.

Liav Ben Artsi

Dan Azeroual

Ido Bourstein

Shimon Avitan

Miki Moyal

David Katz

Ram Ben Ezra

An electrical circuit board assembly includes: (I) a surface, having a plurality of terminals disposed thereon for transferring a power signal to an electronic device, (II) at least first and second layers separated by at least one dielectric layer, the first and second layers being configured to (a) be connected to the power signal, and (b) electrically conduct at least a portion of the power signal, and (III) multiple vias that (i) mechanically traverse the first and second layers at respective traversal points, and (ii) are electrically connected to the terminals on the surface, the multiple vias including: first vias that, at the respective traversal points, are electrically connected to the first layer and electrically isolated from the second layer, and second vias that, at the respective traversal points, are electrically connected to the second layer and electrically isolated from the first layer.

Controlling uniformity of electrical current distribution in device for power delivery to integrated circuit

A printed circuit board (PCB) is provided herein, including signal and ground pads on a surface of the PCB. The signal pads are grouped into differential signal pad pairs, where each differential signal pad pair has a midpoint located halfway between the centers of the signal pads of the differential signal pad pair. A first differential signal pad pair is positioned on a first line, which intersects with both centers of the signal pads of the first differential signal pad pair. A second differential signal pad pair is positioned on a second line, which intersects with the centers of the signal pads of the second differential signal pad pair, parallel to the first line. Additionally, at least one ground pad is positioned along a line drawn from a midpoint of the first differential signal pad pair and a midpoint of the second differential signal pad pair.

Pad and via pattern arrangement for differential signal shielding

A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.

IC package with top-side memory module

An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.

Integrated circuit package differential pin pattern for cross-talk reduction

An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.

Physical layer parameter compliance in high speed communication networks

A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.

Power supply noise reduction circuit and power supply noise reduction method

Systems and methods are provided for an equalizer. An equalizer includes a first voltage correcting circuit configured to correct a communication signal by applying a first variable corrective voltage to the communication signal, the first corrective voltage having a voltage level selected according to a first adjustable granularity. A second voltage correcting circuit is configured to further correct the communication signal by applying a second variable corrective voltage to the communication signal, the second corrective voltage having a voltage level selected according to a second adjustable granularity that is different from the first adjustable granularity.

Systems and methods for reducing quantization errors using adjustable equalizer granularities

Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.

Method and apparatus for reducing jitter

Aspects of the disclosure provide a ball grid array (BGA) package. The ball grid array (BGA) package includes an integrated circuit (IC) packaged in the BGA package, first solder ball, a second solder ball and a third solder ball to transmit a first signal, a second signal, and a third signal. The first signal and the second signal are a pair of differential signals. The third solder ball has a substantially equal distance from the first solder ball and the second solder ball, and thus the first solder ball and the second solder ball are in symmetry with regard to the third solder ball.

Ball-out for differential signals

A system and process overcomes the influence of induced current and/or capacitance in wires and, more particularly, reduces and overcomes induced current and/or capacitance cross-talk between neighboring wire-bonds. A change or toggle in each of a plurality of outputs from a circuit is determined. The change determined for one selected output is compared with the change determined for neighboring outputs. When the change for the neighboring outputs is both the same as that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is increased. When the change for the neighboring outputs is both the opposite of that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is decreased.

System and process for overcoming wire-bond originated cross-talk

The present disclosure provides for a circuit package that can include a signal input port that receives an electronic signal that includes multiple frequency components and a signal output port that outputs the electronic signal. The circuit package can include a trace having multiple portions that have a portion-dependent impedance. The trace can transfer the electronic signal from the signal input port to the signal output port. The present disclosure provides an apparatus to compensate a package trace parasitics, such as parasitic capacitance, to improve signal fidelity over a predetermined frequency range. The apparatus can provide a broadband impedance matching structure that matches the impedance of an I/O cell to the impedance of a printed circuit board and can compensates for the parasitic effects of both the I/O cell, terminals, and other discontinuities that may be present within the package.

Impedance discontinuity compensator for electronic packages

Aspects of the disclosure provide a connector. The connector includes a first signal conductor. The first signal conductor is configured to receive a first electronic signal that includes multiple frequency components. The first signal conductor includes a plurality of conductor portions having portion-dependent impedances. The first signal conductor is configured to transfer the first electronic signal between a via on a circuit board that has a via stub and an electronic device to reduce via stub effects. In addition, in an example, the connector includes a second signal conductor to transfer a second electronic signal. The second electronic signal and the first electronic signal are a pair of differential signals. In an example, the first signal conductor and the second signal conductor have different via stub effects. The first signal conductor and the second signal conductor are configured with regard to each other to have portion-dependent differential impedances to mitigate the different via stub effects.

Connector based compensation of via stub effects

Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry includes input/output (I/O) pads having I/O signal lines coupled thereto, and a capacitor having terminals coupled to the I/O pads and/or signal lines. The method includes transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, to reduce the effect(s) of cross talk in the second I/O signal line. The present invention can significantly reduce the effects of cross talk in neighboring I/O signal paths, for both input and output signals.

Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds

Embodiments of the present disclosure provide an integrated circuit, comprising a first feed forward equalizing (FFE) circuit configured to operate based on receipt of a first common mode voltage; a second FFE circuit coupled to the first FFE circuit, the second FFE circuit configured to operate based on receipt of a second common mode voltage that is different than the first common mode voltage; and a decision circuit coupled to both the first FFE circuit and the second FFE circuit, the decision circuit configured to selectively provide the first common mode voltage to the first FFE circuit or the second common mode voltage to the second FFE circuit.

Growing community of inventors

Nahariya, Israel

Liav Ben Artsi